Effective December 2015 Technical Data 4362 Supersedes January 2012 CPL,CPLA, and CPLE Multi-phase power inductors Applications • For exclusive use with Volterra® or Maxim® VPR-Devices Environmental Data • Storage temperature range (component): -40°C to +125°C • Operating temperature range: -40°C to +125°C (ambient plus self-temperature rise) • Solder reflow temperature: J-STD-020D compliant HALOGEN Product description HF Pb • High current multi-phase inductor applications FREE • 50nH per phase coupled inductor Volterra® is a registered trademark of Volterra Semiconductor, LLC. • CPLA Family features acoustic noise dampening Maxim® is a registered trademark of Maxim Integrated Devices, Inc. properties • CPLE Family features optimized core material for enhanced light load efficiency • Ferrite core material • Frequency range up to 2MHz • Patents pending • Halogen free, lead free and RoHS compliant CPL,CPLA, and CPLE Technical Data 4362 Effective December 2015 Multi-phase power inductors Product Specifications Function Specifications Test Specifications Magnetizing 2 DCR (Ω) DCR (Ω) Rated I Rated Inductance 3 Inductor Nom. Max. Inductance per per Phase Pin 1,2 Pin 1,2 (nH) @ 5ADC OCL OCL 4,5 3 Part Number phases @25°C @25°C Phase (nH) (ADC) numbers (nH) numbers (nH) (25°C) CPL Family—Standard CPL-2-50TR-R 2 0.0005 0.0006 50 ± 20% 40 (1-2) 365 ±18% (3-4) 365 ±18% 300 CPL-3-50TR-R 3 0.0005 0.0006 50 ± 20% 40 (3-4) 490 ±20% (1-2), (5-6) 365 ±18% 400 CPL-4-50TR-R 4 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6) 490 ±20% (1-2), (7-8) 365 ±18% 400 CPL-5-50TR-R 5 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6), (7-8) 490 ±20% (1-2), (9-10) 365 ±18% 400 CPL-6-50TR-R 6 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6), 490 ±20% (1-2), (11- 365 ±18% 400 (7-8), (9-10) 12) CPLA Family—Acoustic Noise Dampening CPLA-2-50TR-R 2 0.0005 0.0006 50 ± 20% 40 (1-2) 365 ±18% (3-4) 365 ±18% 300 CPLA-3-50TR-R 3 0.0005 0.0006 50 ± 20% 40 (3-4) 490 ±20% (1-2), (5-6) 365 ±18% 400 CPLA-4-50TR-R 4 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6) 490 ±20% (1-2), (7-8) 365 ±18% 400 CPLA-5-50TR-R 5 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6), (7-8) 490 ±20% (1-2), (9-10) 365 ±18% 400 CPLE Family—Low Core Loss for Light Load Efficiency CPLE-2-50TR-R 2 0.0005 0.0006 50 ± 20% 40 (1-2) 365 ±18% (3-4) 365 ±18% 300 CPLE-3-50TR-R 3 0.0005 0.0006 50 ± 20% 40 (3-4) 490 ±20% (1-2), (5-6) 365 ±18% 400 CPLE-4-50TR-R 4 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6) 490 ±20% (1-2), (7-8) 365 ±18% 400 CPLE-5-50TR-R 5 0.0005 0.0006 50 ± 20% 40 (3-4), (5-6), (7-8) 490 ±20% (1-2), (9-10) 365 ±18% 400 1. OCL (Open Circuit Inductance) 5. This device is licensed for use only when incorporated within a voltage regulator employing power regulating 2. Test parameters: 1MHz, 0.1Vrms, 0.0Adc. @25°C devices manufactured by Volterra Semiconductor, LLC or Maxim Integrated Devices, Inc. No license is granted 3. The rated current and rated inductance per phase is determined by Volterra’s testing and circuit design. Additional expressly or by implication to use this device with power regulating devices manufactured by any company other information can be provided by contacting Volterra. than Volterra or Maxim. 4. Part Number Definition: CPLx-y-50TR-R-50TR-R • CPLx= Product code and size - CPL (standard)/CPLA (acoustic dampening)/CPLE (low core loss) • -y= number of phases • -50 = rated inductance value per phase in nH • TR= Tape and reel • -R suffix= RoHS compliant www.eaton.com/elx 2 CPL,CPLA, and CPLE Technical Data 4362 Effective December 2015 Multi-phase power inductors Dimensions (mm) 8.50 Max 8.50 Max 8.50 Max Side View 36.0±0.5 18.0±0.5 27.0±0.5 Front View 4.80 Max 4.80 Max 4.80 Max 12 3 4 56 78 14 2 3 12 3 4 56 7.0 7.0 7.0 Bottom View 1.0 1.0 1.0 3.2 3.2 3.2 5.8 5.8 5.8 8.0 8.0 8.0 10.0 10.0 10.0 Pin #1 Pin #1 Pin #1 12 3 4 12 3 4 56 12 36 4 5 7 8 CPLx-2-50 CPLx-3-50 CPLx-4-50 Top View wwllyy R wwllyy R wwllyy R 8.50 Max 8.50 Max Side View 45.0±0.5 54.2±0.5 Front View 4.80 Max 4.80 Max 12 3 4 56 78 9101112 12 38 4 56 7 9 10 7.0 7.0 Bottom View 1.0 1.0 3.2 3.2 5.8 5.8 8.0 8.0 10.0 10.0 Pin #1 12 3 4 56 7 8 9 10 Pin #1 12 3 4 56 78 910 11 12 CPLx-5-50 CPLx-6-50 TopView wwllyy R wwllyy R Part marking: Pin 1 dot, CPL/CPLA/CPLE= (product code and size), -2,-3,-4,-5, -6= (number of phases), -50 = (inductance value per phase in nH) wwllyy = date code, R = revision level Tolerances are ±0.20 millimeters unless stated otherwise All soldering surfaces to be coplanar within 0.15 millimeter Do not route traces or vias underneath the inductor www.eaton.com/elx 3 CPL,CPLA, and CPLE Technical Data 4362 Effective December 2015 Multi-phase power inductors Pad layouts & schematics (mm) Tolerances are ±0.2mm unless otherwise specified. CPLx-3-50-R CPLx-2-50-R CPLx-4-50-R 16.9 25.9 34.9 9.00 9.00 9.00 Recommended 9.00 9.00 9.00 Pad Layout 1.1 1.1 1.1 7.9 7.9 7.9 1 3 1 3 5 1 3 5 7 Schematic 2 4 2 4 6 8 2 4 6 CPLx-6-50-R CPLx-5-50-R 52.9 43.9 9.00 9.00 Recommended 9.00 Pad Layout 1.1 1.1 7.9 7.9 1 3 5 7 9 1 3 5 7 9 11 Schematic 2 4 6 8 10 2 4 6 8 10 12 www.eaton.com/elx 4 CPLx-4-50 wwllyy R CPLx-2-50 CPLx-3-50 CPLx-5-50 wwllyy R wwllyy R wwllyy R CPLx-6-50 wwllyy R CPL,CPLA, and CPLE Technical Data 4362 Effective December 2015 Multi-phase power inductors Packaging Information (mm) Supplied in tape-and-reel packaging, 750 parts per reel, 13” diameter reel. Pin #1 1.5Dia 2.0 1.75 4.0 14.2 2.0 32.0 28.4 ± 0.3 18.9 CPLx-2-50 ± 0.1 8.9 16.0 5.2 Section A-A Pin #1 4.0 1.5Dia 2.0 1.75 20.2 2.0 40.4 ± 0.1 27.9 CPLx-3-50 44.0 ± 0.3 5.2 8.9 16.0 Section A-A 1.5Dia 2.0 Pin #1 1.75 26.2 4.0 2.0 52.4 ± 0.1 56.0 36.9 CPLx-4-50 ± 0.3 5.2 8.9 16.0 Section A-A Pin #1 1.5Dia 2.0 34.2 4.0 1.75 2.0 72.0 ± 0.3 45.9 CPLx-5-50 68.4 ± 0.1 8.9 16.0 5.2 Pin #1 Section A-A 2.0 1.5Dia 4.0 1.75 34.2 2.0 72.0 ± 0.3 54.9 CPLx-6-50 68.4 ± 0.1 8.9 16.0 5.2 Section A-A User direction of feed www.eaton.com/elx 5 CPL,CPLA, and CPLE Technical Data 4362 Effective December 2015 Multi-phase power inductors Solder reflow profile TP Table 1 - Standard SnPb Solder (T ) c T -5°C C t P Volume Volume Max. Ramp Up Rate = 3°C/s Package mm3 mm3 Max. Ramp Down Rate = 6°C/s Thickness <350 ≥350 T <2.5mm) 235°C 220°C L Preheat t ≥2.5mm 220°C 220°C A Tsmax Table 2 - Lead (Pb) Free Solder (T ) c Volume Volume Volume 3 3 3 T Package mm mm mm smin Thickness <350 350 - 2000 >2000 t s <1.6mm 260°C 260°C 260°C 1.6 – 2.5mm 260°C 250°C 245°C >2.5mm 250°C 245°C 245°C 25°C Time 25°C to Peak Time Reference JDEC J-STD-020D Profile Feature Standard SnPb Solder Lead (Pb) Free Solder Preheat and Soak • Temperature min. (T ) 100°C 150°C smin • Temperature max. (T ) 150°C 200°C smax • Time (T to T ) (t ) 60-120 Seconds 60-120 Seconds smin smax s Average ramp up rate T to T 3°C/ Second Max. 3°C/ Second Max. smax p Liquidous temperature (Tl) 183°C 217°C Time at liquidous (t ) 60-150 Seconds 60-150 Seconds L Peak package body temperature (T )* Table 1 Table 2 P Time (t )** within 5 °C of the specified classification temperature (T ) 20 Seconds** 30 Seconds** p c Average ramp-down rate (T to T ) 6°C/ Second Max. 6°C/ Second Max. p smax Time 25°C to Peak Temperature 6 Minutes Max. 8 Minutes Max. * Tolerance for peak profile temperature (T ) is defined as a supplier minimum and a user maximum. p ** Tolerance for time at peak profile temperature (t ) is defined as a supplier minimum and a user maximum. p Life Support Policy: Eaton does not authorize the use of any of its products for use in life support devices or systems without the express written approval of an officer of the Company. Life support systems are devices which support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Eaton reserves the right, without notice, to change design or construction of any products and to discontinue or limit distribution of any products. Eaton also reserves the right to change or update, without notice, any technical information contained in this bulletin. Eaton Electronics Division 1000 Eaton Boulevard Cleveland, OH 44122 United States www.eaton.com/elx © 2015 Eaton All Rights Reserved Eaton is a registered trademark. Printed in USA Publication No. 4362 BU-SB12070 All other trademarks are property December 2015 of their respective owners. Temperature