LSN2 Series www.murata-ps.com Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters ORDERING GUIDE SUMMARY Model Vout Range Iout Range Vin Range Ripple/Noise Efficiency Typical Unit LSN2-T/6-W3-C 0.75-3.3V 0-6A 2.4-5.5V 15mVp-p 94% LSN2-T/6-D12 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12-C 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12G 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12-GC 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12N 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12-NC 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12NG 0.75-5V 0-6A 8.3-14V 15mVp-p 93% LSN2-T/6-D12-NGC 0.75-5V 0-6A 8.3-14V 15mVp-p 93% FEATURES LSN2-T/10-W3-C 0.75-3.3V 0-10A 2.4-5.5V 15mVp-p 95% ■ User-selectable outputs: 0.75-5V LSN2-T/10-D12-C 0.75-5V 0-10A 8.3-14V 30mVp-p 95% (D12 models) or 0.75-3.3V (W3 models) LSN2-T/16-W3-C 0.75-3.3V 0-16A 2.4-5.5V 25mVp-p 95% ■ 6, 10 or 16A maximum output current LSN2-T/16-D12-C 0.75-5V 0-16A 8.3-14V 30mVp-p 94% ■ Double lead free to RoHS standards INPUT CHARACTERISTICS ■ Selectable phased start-up sequencing Parameter Typ. @ 25°C, full load Notes and tracking ■ Voltage Range 2.4-5.5 or 8.3-14V 5V or 12V nominal models Wide range VIN 8.3-14V or 2.4-5.5V Current, full power 4.22 to 11.12A Model dependent ■ Up to 52 Watts total output power Undervoltage Shutdown Included With autorestart hysteresis ■ Very high efficiency up to 95% Short Circuit Current 60mA Output is short circuited ■ Starts up into pre-biased load Remote On/Off Control Positive or negative polarity Default polarity is positive ■ Fast settling, high di/dt IOUT slew rate OUTPUT CHARACTERISTICS Parameter Typ. @ 25°C, full load Notes PRODUCT OVERVIEW Voltage 0.75-3.3 or 0.75-5V User adjustable, model dependent These miniature point-of-load (POL) switch- Current 0-6, 0-10 or 0-16A Three ranges, model dependent ing DC/DC converters are ideal regulation and Power Dissipation 20, 33, 52W max. Three values, model dependent supply elements for mixed voltage systems. Fully Accuracy ±2% of VNOM 50% load compatible with the Distributed-power Open Standards Alliance specification (www.dosa- Ripple & Noise 15-75mVpp Model dependent power.com), LSN2’s can power CPU’s, program- Line and Load Regulation ±0.03% mable logic and mixed-voltage systems with little Overcurrent Protection Hiccup autorecovery Continuous short circuit protection heat and low noise. A typical application uses a Overtemperature Protection +115°C shutdown master isolated 12 or 5Vdc supply and individual Efficiency (minimum) 92-93% Model dependent LSN2 converters for local 1.8 and 3.3Vdc sup- Efficiency (typical) 94-95% Model dependent plies. All system isolation resides in the central supply, leaving lower cost POL regulation at the GENERAL SPECIFICATIONS load. The LSN2’s can deliver very high power (to Parameter Typ. @ 25°C, full load Notes 52 Watts) in a tiny area without heat sinking or Transient Response 25μsec 50% load step to 2% of final value external components. They feature quick transient Operating Temperature Range –40 to +85°C With 200 lfm airflow response (to 25µsec) and very fast current slew Safety (designed to meet) UL/IEC/EN 60950-1 And CSA C22.2-No.234 rates (to 20A/µsec). EMI (designed to meet) FCC pt.15, class B May need external filter MECHANICAL CHARACTERISTICS Pb 6 Amp output models 0.50 x 1.00 x 0.275 inches (12.7 x 25.4 x 6.98 mm) 10 & 16 Amp models 0.50 x 2.00 x 0.32 inches (12.7 x 50.8 x 8.13 mm) Lead-free construction/attach For full details go to www.murata-ps.com/rohs www.murata-ps.com/support MDC_LSN2.D01∆  Page 1 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters PERFORMANCE SPECIFICATIONS AND ORDERING GUIDE  Output Input Package R/N (mVp-p)  Regulation  Efficiency Vout Iout Power Vin Nom. Range  Iin  (Case/ Root Model  (Volts) (Amps) (Watts) Typ. Max. Line Load (Volts) (Volts) (mA/A) Min. Typ. Pinout) LSN2-T/6-W3 0.75-3.3 6 19.8 25 40 ±0.075% ±0.055% 5 2.4-5.5 50/4.2 93.1% 94.3% B12, P69 LSN2-T/6-D12 0.75-5 6 30 15 25 ±0.3% ±0.3% 12 8.3-14 70/2.69 90% 93% B12, P69 LSN2-T/10-W3 0.75-3.3 10 33.0 15 25 ±0.3% ±0.3% 5 2.4-5.5 50/6.95 93% 95% B11, P68 LSN2-T/10-D12 0.75-5 10 50 30 75 ±0.3% ±0.3% 12 8.3-14 100/4.39 93% 95% B11, P68 LSN2-T/16-W3 0.75-3.3 16 52.8 25 50 ±0.3% ±0.3% 5 2.4-5.5 50/11.12 93% 95% B11, P68 LSN2-T/16-D12 0.75-5 16 80 30 75 ±0.3% ±0.3% 12 8.3-14 100/7.1 92% 94% B11, P68 LSN2-T/30-D12 0.8-5 30 150 Please refer to the separate LSN2-T/30 data sheet. ➀ Typical at Ta = +25°C under nominal line voltage and full-load conditions, unless noted. All models ➂ These devices have no minimum-load requirements and will regulate under no-load conditions. Regula- are tested and specified with external 22µF tantalum input and output capacitors. These capacitors tion specifications describe the output-voltage deviation as the line voltage or load is varied from its are necessary to accommodate our test equipment and may not be required to achieve specified nominal/midpoint value to either extreme. performance in your applications. See I/O Filtering and Noise Reduction. “Nominal” output is 3.3V ➃ Nominal line voltage, no-load/full-load conditions. (W3 models) or 5V (D12 models) ➄ VIN must be ≥0.5V greater than VOUT. ➁ Ripple/Noise (R/N) is tested/specified over a 20MHz bandwidth and may be reduced with external ➅ LSN2-TXX-D12 efficiencies are shown at 5VOUT. filtering. See I/O Filtering and Noise Reduction for details. ➆ These are not complete model numbers. Please refer to the Part Number Structure when ordering. PART NUMBER STRUCTURE L SN2 -T /16 -D12 N G -C RoHS-6 hazardous substance compliant Output Configuration: L = Unipolar Low Voltage Power Good Output:  ➂ These devices have no minimum-load requirements and will regu- late under no-load conditions. Regulation specifications describe Blank = Omitted the output-voltage deviation as the line voltage or load is varied G = Installed from its nominal/midpoint value to either extreme. Non-Isolated Through-hole ➃ Nominal line voltage, no-load/full-load conditions. ➄ VIN must be ≥0.5V greater than VOUT. On/Off Polarity: Nominal Output Voltage: ➅ LSN2-TXX-D12 efficiencies are shown at 5VOUT. Blank = Positive polarity ➆ These are not complete model numbers. Please refer to the 0.75-3.3 Volts (W3) N = Negative polarity Part Number Structure when ordering. 0.75-5 Volts (D12) Maximum Rated Output: Input Voltage Range: Note: Current in Amps Some model number combinations may D12 = 8.3-14 Volts (12V nominal) not be available. Contact Murata Power W3 = 2.4-5.5 Volts (5V nominal) Solutions for further information. www.murata-ps.com/support MDC_LSN2.D01∆  Page 2 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A (1) Selectable-Output DC/DC Converters Performance/Functional Specifications Current Limit Inception: (98% of V ) out INPUT LSN2-T/6 models 11-13 Amps (cold startup) Input Voltage Range See Ordering Guide 11 Amps (after warm up) Isolation Not isolated, input and output commons LSN2-T/10 models 18.75 Amps (cold startup) are internally connected 16.75 Amps (after warm up) Start-Up Threshold LSN2-T/16 models 24 Amps (cold startup) W3 Models 2.2 Volts 21 Amps (after warm up) 12V Models 8 Volts (6) Short Circuit Mode Undervoltage Shutdown Short Circuit Current Output 600mA W3 Models 2.0 Volts (17) Protection Method Hiccup autorecovery on overload removal 12V Models 7.5 Volts Short Circuit Duration Continuous, no damage (output shorted Overvoltage Shutdown None to ground) (16) (2) Prebias Startup Converter will start up if the external Reflected (Back) Ripple Current 10-70mAp-p (model dependent) output voltage is less than Vnom Internal Input Filter Type Capacitive Sequencing Slew Rate 2V max. per millisecond Reverse Polarity Protection See fuse information Startup delay until sequence start 10 milliseconds Input Current: Tracking accuracy, rising input Vout = ±100mV of Sequence In Full Load Conditions See Ordering Guide Tracking accuracy, falling input Vout = ±200mV of Sequence In 2 Inrush Transient 0.1A sec Sequence pin input impedance 400kW to 1MW Shutdown Mode (Off, UV, OT) 5mA (7) Remote Sense to Vout 0.5V max. Output Short Circuit 60mA (14) Power Good Output TRUE (OK) = open drain No Load (“G” suffix) FALSE (not OK) = Signal Ground to 0.4V W3 models 50mA Power_Good Configuration MOSFET to ground with external user 12V models 100mA pullup, 10mA max. sink Low Line (Vin = Vmin) DYNAMIC CHARACTERISTICS LSN2-T/6-W3 5.54 Amps LSN2-T/6-D12 3.85 Amps Dynamic Load Response 25µsec to ±2% of final value LSN2-T/10-W3 9.14 Amps (50-100-50% load step, di/dt = 20A/msec) LSN2-T/10-D12 6.31 Amps Start-Up Time 4-7msec for Vout = nominal LSN2-T/16-W3 14.63 Amps (Vin on to Vout regulated or On/Off to Vout) LSN2-T/16-D12 10.2 Amps Switching Frequency (5) Remote On/Off Control: LSN2-T/6 models 315kHz Positive Logic (no model suffix) OFF = ground pin to +0.8V max. LSN2-T/10 and -T/16 models 230kHz ON = open pin or +2.5V min. to +Vin max. Negative Logic (“N” model suffix) ON = open pin to +0.3V max. ENVIRONMENTAL OFF = +2.5V min. to +Vin max. (4) Calculated MTBF TBC Hours Current 1mA max. Operating Temperature Range (Ambient) (9) No derating, natural convection –40 to +63°C, vertical mount, 2.5Vout OUTPUT With derating See Derating Curves Voltage Output Range See Ordering Guide (12) Operating PC Board Temperature –40 to +100°C max. Minimum Loading No minimum load Storage Temperature Range –55 to +125°C Accuracy (50% load) ±2% of Vnom Thermal Protection/Shutdown +115°C (13) Relative Humidity To +85% / +85°C Voltage Adjustment Range  See Ordering Guide PHYSICAL Temperature Coefficient ±0.02% of Vout range per °C (8) Outline Dimensions See Mechanical Specifications Ripple/Noise (20 MHz bandwidth) See Ordering Guide and (10) Removable Heat Shield Nylon 46 Line/Load Regulation (See Tech Notes) See Ordering Guide and Pin Material  Tin-plated copper alloy Efficiency See Ordering Guide (15) Weight 0.28 ounces (7.8 grams) Maximum Capacitive Loading: Electromagnetic Interference FCC part 15, class B, EN55022 LSN2-T/6 models: Cap-ESR = 0.001 to 0.01W 3000µF (conducted and radiated) (may need external filter) Cap-ESR >0.01W 5000µF Safety UL/cUL 60950-1, CSA-C22.2 No.234 LSN2-T/10 and -T/16 models: IEC/EN 60950-1 Cap-ESR = 0.001 to 0.01W 5000µF Flammability Rating UL94V-0 Cap-ESR >0.01W 10,000µF www.murata-ps.com/support MDC_LSN2.D01∆  Page 3 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters ABSOLUTE MAXIMUM RATINGS PERFORMANCE/FUNCTIONAL SPECIFICATION NOTES Input Voltage (Continuous or transient) (1) All models are tested and specified with external 1 || 10µF ceramic/tantalum output capacitors and a 22µF external input capacitor. All capacitors are low ESR types. These capacitors are necessary W3 models +7 Volts to accommodate our test equipment and may not be required to achieve specified performance in 12V models +15 Volts your applications. All models are stable and regulate within spec under no-load conditions. On/Off Control –0.3V min. to +VIN max. General conditions for Specifications are +25°C, VIN = nominal, VOUT = nominal, full load. “Nominal” Input Reverse Polarity Protection See Fuse section output voltage is +5V for D12 models and +3.3V for W3 models. (2) Input Back Ripple Current is tested and specified over a 5-20MHz bandwidth. Input filtering is Output Current (7) Current-limited. Devices can CIN = 2 x 100µF tantalum, CBUS = 1000µF electrolytic, LBUS = 1µH. withstand sustained short circuit (3) Note that Maximum Power Derating curves indicate an average current at nominal input voltage. At without damage. higher temperatures and/or lower airflow, the DC/DC converter will tolerate brief full current outputs Storage Temperature –55 to +125°C if the total RMS current over time does not exceed the derating curve. (4) Mean Time Before Failure is calculated using the Telcordia (Belcore) SR-332 Method 1, Case 3, Lead Temperature See soldering guidelines ground fixed conditions, TPCBOARD = +25°C, full output load, natural air convection. These are stress ratings. Exposure of devices to greater than any of these conditions may (5) The On/Off Control may be driven with external logic or by applying appropriate external voltages adversely affect long-term reliability. Proper operation under conditions other than those listed in which are referenced to –Input Common. The On/Off Control Input should use either an open the Performance/Functional Specifications Table is not implied. collector/open drain transistor or logic gate which does not exceed +VIN. A 68KW external pullup resistor to +VIN will cause the “ON” state for negative logic models. (6) Short circuit shutdown begins when the output voltage under increasing load degrades approxi- mately 2% from the selected setting. (7) If Sense is connected remotely at the load, up to 0.5 Volts difference is allowed between the Sense Soldering Guidelines and +VOUT pins to compensate for ohmic voltage drop in the power lines. A larger voltage drop may Murata Power Solutions recommends the specifications below when installing these cause the converter to exceed maximum power dissipation. (8) converters. These specifications vary depending on the solder type. Exceeding these Output noise may be further reduced by adding an external filter. See I/O Filtering and Noise Reduction. (9) All models are fully operational and meet published specifications, including “cold start” at –40°C. specifications may cause damage to the product. Be cautious when there is high atmo- VOUT is nominal. spheric humidity. We strongly recommend a mild pre-bake (100° C. for 30 minutes). Your (10) Regulation specifications describe the deviation as the line input voltage or output load current is production environment may differ; therefore please thoroughly review these guidelines varied from a nominal midpoint value to either extreme. with your process engineers. (11) Other input or output voltage ranges are available under scheduled quantity special order. (12) Maximum PC board temperature is measured with the sensor in the center. Wave Solder Operations for through-hole mounted products (THMT)  (13) Do not exceed maximum power specifications when adjusting the output trim. (14) For Sn/Ag/Cu based solders: When Sequencing is not used, the Power Good output is TRUE at any time the output is within approximately ±10% of the voltage set point. Power Good basically indicates if the converter is in Maximum Preheat Temperature 115° C. regulation. Power Good detects Over Temperature if the PWM has shut down due to OT. Power Good does not directly detect Over Current. Maximum Pot Temperature 270° C. If Sequencing is in progress, Power Good will falsely indicate TRUE (valid) before the output Maximum Solder Dwell Time 7 seconds reaches its setpoint. Ignore Power Good if Sequencing is in transition. (15) The maximum output capacitive loads depend on the the Equivalent Series Resistance (ESR) of For Sn/Pb based solders: the external output capacitor. Maximum Preheat Temperature 105° C. (16) Do not use Pre-bias startup and sequencing together. See Technical Notes below. (17) After short circuit shutdown, if the load is partially removed such that the load still exceeds the Maximum Pot Temperature 250° C. overcurrent (OC) detection, the converter will remain in hiccup restart mode. Maximum Solder Dwell Time 6 seconds (18) For best noise performance, leave the Track/Sequence pin OPEN when not used. www.murata-ps.com/support MDC_LSN2.D01∆  Page 4 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters +OUTPUT +INPUT 10.5Ω +SENSE COMMON COMMON VCC PWM CURRENT ON/OFF CONTROLLER SENSE CONTROL REFERENCE & VTRACK VOUT ERROR AMP INPUT TRIM Figure 1. LSN2 Series Simplified Schematic Typical topology is shown TECHNICAL NOTES I/O Filtering and Noise Reduction In critical applications, input/output ripple/noise may be further reduced using All models in the LSN2 Series are tested and specified with external 1 || 10µF filtering techniques, the simplest being the installation of external I/O caps. ceramic/tantalum output capacitors and a 22µF tantalum input capacitor. External input capacitors serve primarily as energy-storage devices. They These capacitors are necessary to accommodate our test equipment and minimize high-frequency variations in input voltage (usually caused by IR may not be required to achieve desired performance in your application. The drops in conductors leading to the DC/DC) as the switching converter draws LSN2's are designed with high-quality, high-performance internal I/O caps, pulses of current. Input capacitors should be selected for bulk capacitance and will operate within spec in most applications with no additional external (at appropriate frequencies), low ESR, and high rms-ripple-current ratings. components. The switching nature of modern DC/DCs requires that the dc input voltage In particular, the LSN2's input capacitors are specified for low ESR and are source have low ac impedance at the frequencies of interest. Highly inductive fully rated to handle the units' input ripple currents. Similarly, the internal out- source impedances can greatly affect system stability. Your specific system put capacitors are specified for low ESR and full-range frequency response. configuration may necessitate additional considerations. www.murata-ps.com/support MDC_LSN2.D01∆  Page 5 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters Safety Considerations TO LSN2 SIPs are non-isolated DC/DC converters. In general, all DC/DC’s must CURRENT OSCILLOSCOPE PROBE be installed, including considerations for I/O voltages and spacing/separation 2 +INPUT requirements, in compliance with relevant safety-agency specifications (usually LBUS + UL/IEC/EN60950-1). VIN CBUS CIN In particular, for a non-isolated converter’s output voltage to meet SELV – (safety extra low voltage) requirements, its input must be SELV compliant. If 3 COMMON the output needs to be ELV (extra low voltage), the input must be ELV. CIN = 2 x 100µF, ESR < 700mΩ @ 100kHz Input Overvoltage and Reverse-Polarity Protection CBUS = 1000µF, ESR < 100mΩ @ 100kHz LBUS = 1µH LSN2 SIP Series DC/DCs do not incorporate either input overvoltage or input reverse-polarity protection. Input voltages in excess of the specified absolute Figure 2. Measuring Input Ripple Current maximum ratings and input polarity reversals of longer than “instantaneous” duration can cause permanent damage to these devices. Output ripple/noise (also referred to as periodic and random deviations or Start-Up Time PARD) may be reduced below specified limits with the installation of additional The VIN to VOUT Start-Up Time is the interval between the time at which a external output capacitors. Output capacitors function as true filter elements ramping input voltage crosses the lower limit of the specified input voltage and should be selected for bulk capacitance, low ESR, and appropriate fre- range and the fully loaded output voltage enters and remains within its speci- quency response. Any scope measurements of PARD should be made directly fied accuracy band. Actual measured times will vary with input source imped- at the DC/DC output pins with scope probe ground less than 0.5" in length. ance, external input capacitance, and the slew rate and final value of the input All external capacitors should have appropriate voltage ratings and be located voltage as it appears to the converter. as close to the converters as possible. Temperature variations for all relevant parameters should be taken into consideration. The On/Off to VOUT Start-Up Time assumes the converter is turned off via the On/Off Control with the nominal input voltage already applied to the converter. The specification defines the interval between the time at which the converter is turned on and the fully loaded output voltage enters and remains within its COPPER STRIP +SENSE specified accuracy band. See Typical Performance Curves. +OUTPUT Remote Sense  LSN2 Series offer an output sense function. The sense function enables RLOAD SCOPE C1 C2 point-of-use regulation for overcoming moderate IR drops in conductors and/ or cabling. Since these are non-isolated devices whose inputs and outputs usually share the same ground plane, sense is provided only for the +Output. COMMON COPPER STRIP The remote sense line is part of the feedback control loop regulating the DC/ DC converter’s output. The sense line carries very little current and consequent- C1 = 1µF CERAMIC ly requires a minimal cross-sectional-area conductor. As such, it is not a low- C2 = 10µF TANTALUM impedance point and must be treated with care in layout and cabling. Sense LOAD 2-3 INCHES (51-76mm) FROM MODULE lines should be run adjacent to signals (preferably ground), and in cable and/or discrete-wiring applications, twisted-pair or similar techniques should be used. Figure 3. Measuring Output Ripple/Noise (PARD) The sense function is capable of compensating for voltage drops between The most effective combination of external I/O capacitors will be a function the +Output and +Sense pins that do not exceed 10% of VOUT. of your line voltage and source impedance, as well as your particular load and layout conditions. [VOUT(+) – Common] – [Sense(+) – Common] ≤ 10%VOUT Input Fusing Power derating (output current limiting) is based upon maximum output current and voltage at the converter's output pins. Use of trim and sense Most applications and or safety agencies require the installation of fuses functions can cause the output voltage to increase, thereby increasing output at the inputs of power conversion components. The LSN2 Series are not power beyond the LSN2's specified rating. Therefore: internally fused. Therefore, if input fusing is mandatory, either a normal-blow or a slow-blow fuse with a value no greater than twice the maximum input (VOUT at pins) x (IOUT) ≤ rated output power current calculated at low line with the converter's minimum efficiency should be installed within the ungrounded input path to the converter. The internal 10.5W resistor between +Sense and +Output (see Figure 1) serves to protect the sense function by limiting the output current flowing www.murata-ps.com/support MDC_LSN2.D01∆  Page 6 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters through the sense line if the main output is disconnected. It also prevents Output Overvoltage Protection output voltage runaway if the sense connection is disconnected. LSN2 SIP Series DC/DC converters do not incorporate output overvoltage pro- tection. In the extremely rare situation in which the device’s feedback loop is Note: If the sense function is not used for remote regulation, +Sense broken, the output voltage may run to excessively high levels (VOUT = VIN). If it must be tied to +Output at the DC/DC converter pins. is absolutely imperative that you protect your load against any and all possible overvoltage situations, voltage limiting circuitry must be provided external to Remote On/Off Control the power converter. The input-side remote On/Off Control is an external input signal available in either positive (no suffix) or negative (“N” suffix) polarity. Normally this input is controlled by the user’s external transistor or relay. With simple external +INPUT circuits, it may also be selected by logic outputs. Please note however that the actual control threshold levels vary somewhat with the PWM supply and therefore are best suited to “open collector” or “open drain” type logic. The 10kΩ +V On/Off control takes effect only when appropriate input power has been ap- ON/OFF plied and stabilized (approximately 7msec). CONTROL EXTERNAL SHUTDOWN OPEN COLLECTOR For positive polarity, the default operation leaves this pin open (unconnected) SIGNAL INPUT GROUND CONTROLLER or HIGH. The output will then always be on (enabled) whenever appropriate input power is applied. Negative polarity models require the On/Off to be COMMON grounded to the –Input terminal or brought LOW to turn the converter on. To turn the converter off, for positive polarity models, ground the On/Off Figure 5. Inverting On/Off Control control or bring it LOW. For negative polarity, raise the On/Off at least to +2.5V to turn it off. Output Overcurrent Detection Dynamic control of the On/Off must be capable of sinking or sourcing the Overloading the power converter's output for an extended time will invariably control current (approximately 1mA max.) and not overdrive the input greater cause internal component temperatures to exceed their maximum ratings and than the +VIN power input. Always wait for the input power to stabilize before eventually lead to component failure. High-current-carrying components such activating the On/Off control. Be aware that a delay of several milliseconds as inductors, FET's and diodes are at the highest risk. LSN2 SIP Series DC/DC occurs (see specifications) between activation of the control and the resulting converters incorporate an output overcurrent detection and shutdown function change in the output. that serves to protect both the power converter and its load. Power-up sequencing If the output current exceeds it maximum rating by typically 50% or if the If a controlled start-up of one or more LSN2 Series DC/DC converters is required, output voltage drops to less than 98% of it original value, the LSN2's internal or if several output voltages need to be powered-up in a given sequence, the overcurrent-detection circuitry immediately turns off the converter, which then On/Off control pin can be driven with an external open collector device as per goes into a “hiccup” mode. While hiccupping, the converter will continuously Figure 4. attempt to restart itself, go into overcurrent, and then shut down. Once the output short is removed, the converter will automatically restart itself. Output Reverse Conduction Many DC/DCs using synchronous rectification suffer from Output Reverse +INPUT Conduction. If those devices have a voltage applied across their output before a voltage is applied to their input (this typically occurs when another power supply starts before them in a power-sequenced application), they will either +V ON/OFF fail to start or self destruct. In both cases, the cause is the “freewheeling” or SMALL CONTROL SHUTDOWN SIGNAL “catch” FET biasing itself on and effectively becoming a short circuit. TRANSISTOR SIGNAL HI = OFF GROUND LSN2 SIP DC/DC converters do not suffer from Output Reverse Conduction. CONTROLLER LO = ON They employ proprietary gate drive circuitry that makes them immune to COMMON moderate applied output overvoltages. Thermal Considerations and Thermal Protection The typical output-current thermal-derating curves shown below enable Figure 4. On/Off Control Using An External Open Collector Driver designers to determine how much current they can reliably derive from each Leaving the input of the on/off circuit closed during power-up will have the model of the LSN2 SIPs under known ambient-temperature and air-flow con- output of the DC/DC converter disabled. When the input to the external open ditions. Similarly, the curves indicate how much air flow is required to reliably collector is pulled high, the DC/DC converter’s output will be enabled. deliver a specific output current at known temperatures. www.murata-ps.com/support MDC_LSN2.D01∆  Page 7 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters never absolutely constant, the converter may start up at some times and not The highest temperatures in LSN2 SIPs occur at their output inductor, 2 whose heat is generated primarily by I R losses. The derating curves were at others. developed using thermocouples to monitor the inductor temperature and Solutions varying the load to keep that temperature below +110°C under the assorted To improve start up, review the conditions above. One of the better solutions conditions of air flow and air temperature. Once the temperature exceeds is to place a moderate size capacitor very close to the input terminals. You +115°C (approx.), the thermal protection will disable the converter. Automatic may need two parallel capacitors. A larger electrolytic or tantalum cap sup- restart occurs after the temperature has dropped below +110°C. plies the surge current and a smaller parallel low-ESR ceramic cap gives low As you may deduce from the derating curves and observe in the efficiency AC impedance. Too large an electrolytic capacitor may have higher internal curves on the following pages, LSN2 SIPs maintain virtually constant efficien- impedance (ESR) and/or lower the start up slew rate enough to upset the DC/ cy from half to full load, and consequently deliver very impressive temperature DC’s controller. Make sure the capacitors can tolerate reflected switching cur- performance even if operating at full load. rent pulses from the converter. Lastly, when LSN2 SIPs are installed in system boards, they are obviously The capacitors will not help if the input source has poor regulation. A subject to numerous factors and tolerances not taken into account here. If you converter which starts successfully at 3.3 Volts will turn off if the input voltage are attempting to extract the most current out of these units under demand- decays to below the input voltage theshold, regardless of external capacitance. ing temperature conditions, we advise you to monitor the output-inductor Increase the input start up voltage if possible to raise the downward voltage temperature to ensure it remains below +110°C at all times. spike. Also, make sure that the input voltage ramps up in a reasonably short Start Up Considerations time (less than a few milliseconds). If possible, move the input source closer When power is first applied to the DC/DC converter, operation is different than to the converter to reduce ohmic losses in the input wiring. Remember that when the converter is running and stabilized. There is some risk of start up the input current is carried both by the wiring and the ground plane return. difficulties if you do not observe several application features. Lower output Make sure the ground plane uses adequate thickness copper. Run additional voltage converters may have more problems here since they tend to have bus wire if necessary. higher output currents. Operation is most critical with any combination of the Any added output capacitor should use just enough capacitance (and following external factors: no more) to reduce output noise at the load and to avoid marginal thresh- 1 – Low initial input line voltage and/or poor regulation of the input source. old noise problems with external logic. An output cap will also “decouple” 2 – Full output load current on lower output voltage converters. inductive reactance in the load. Certain kinds of electronic loads include “constant current” characteristics which destabilize the output with insuf- 3 – Slow slew rate of input voltage. ficient capacitance. If the wiring to the eventual load is long, consider placing 4 – Longer distance to input voltage source and/or higher external input this decoupling cap at the load. Use the Remote Sense input to avoid ohmic source impedance. voltage drop errors. 5 – Limited or insufficient ground plane. External wiring that is too small. An elegant solution to start up problems is to apply the input voltage with 6 – Too small external input capacitance. Too high ESR. the Remote On/Off control first in the off setting (for those converters with an 7 – High output capacitance causing a start up charge overcurrent surge. On/Off Control). After the specified start-up delay (usually under 20 mSec), turn on the converter. The controller will have already been stabilized. The 8 – Output loads with excessive inductive reactance or constant current short delay will not be noticed in most applications. Be aware of applications characteristics. which need “power management” (phased start up). If the input voltage is already at the low limit before power is applied, the Finally, it is challenging to model some application circuits with absolute start up surge current may instantaneously reduce the voltage at the input fidelity. How low is the resistance of your ground plane? What is the inductance terminals to below the specified minimum voltage. Even if this voltage depres- (and distributed capacitance) of external wiring? Even a detailed mathematical sion is very brief, this may interfere with the on-board controller and possibly model may not get all aspects of your circuit. Therefore it is difficult to give cap cause a failed start. Or the converter may start but the input current load will values which serve all applications. Some experimentation may be required. now drive the input voltage below its running low limit and the converter will shut down. Pre-Biased Startup If you measure the input voltage before start up with a Digital Voltmeter (DVM), Newer systems with multiple power voltages have an additional problem the voltage may appear to be adequate. Limited external capacitance and/or besides startup sequencing. Some sections have power already partially ap- too high a source impedance may cause a short downward spike at power up, plied (possibly because of earlier power sequencing) or have leakage power causing an instantaneous voltage drop. Use an oscilloscope not a DVM to observe present so that the DC/DC converter must power up into an existing voltage. this spike. The converter’s soft-start controller is sensitive to input voltage. What This power may either be stored in an external bypass capacitor or supplied matters here is the actual voltage at the input terminals at all times. by an active source. Symptoms of start-up difficulties may include failed started, output oscil- This “pre-biased” condition can also occur with some types of program- lation or brief start up then overcurrent shutdown. Since the input voltage is mable logic or because of blocking diode leakage or small currents passed www.murata-ps.com/support MDC_LSN2.D01∆  Page 8 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters through forward biased ESD diodes. Conventional DC/DC’s may fail to start up D12 Models Resistor Trim Equation: correctly if there is output voltage already present. And some external circuits 10500 are adversely affected when the low side MOSFET in a synchronous rectifier _____________ RTRIM (W) = – 1000 converter sinks current at start up. VO – 0.7525 The LSN2 series includes a pre-bias startup mode to prevent these initializa- Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5V tion problems. Essentially, the converter acts as a simple buck converter until Rtrim (kΩ) Open 41.424 22.46 13.05 9.024 5.009 3.122 1.472 the output reaches its set point voltage at which time it converts to a synchro- nous rectifier design. This feature is variously called “monotonic” because the Voltage Trim voltage does not decay (from low side MOSFET shorting) or produce a negative The LSN2 Series may also be trimmed using an external voltage applied transient once the input power is applied and the startup sequence begins. between the Trim input and Output Common. Be aware that the internal “load” impedance looking into trim pin is approximately 5kW. Therefore, you may Don’t Use Pre-Biasing and Sequencing Together have to compensate for this in the source resistance of your external voltage Normally, you would use startup sequencing on multiple DC/DC’s to solve the reference. Pre-Bias problem. By causing all power sources to ramp up together, no one source can dominate and force the others to fail to start. For most applica- Use a low noise DC reference and short leads. Mount the leads close to the tions, do not use startup sequencing in a Pre-Bias application, especially with converter. an external active power source. Two different trim equations are used for the W3 and D12 models. If you have active source pre-biasing, leave the Sequence input open so W3 Models Voltage Trim Equation: that the output will step up quickly and safely. A symptom of this condition is repeated failed starts. You can further verify this by removing the existing load VTRIM (in Volts) = 0.7 – (0.1698 x (VO – 0.7525)) and testing it with a separate passive resistive load which does not exceed full current. If the resistive load starts successfully, you may be trying to drive an The LSN2 W3 fixed trim voltages to set the output voltage are: external pre-biased active source. Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V It may also be possible to use pre-bias and sequencing together if the Pre- Vtrim Open 0.6928V 0.624V 0.5731V 0.5221V 0.4033V 0.267V Bias source is in fact only a small external bypass capacitor slowly charged by leakage currents. Test your application to be sure. D12 Models Voltage Trim Equation: Output Adjustments The LSN2 series includes a special output voltage trimming feature which VTRIM (in Volts) = 0.7 – (0.0667 x (VO – 0.7525)) is fully compatible with competitive units. The output voltage may be varied using a single trim resistor from the Trim input to Power Common (pin 4) or an The LSN2 D12 fixed trim voltages to set the output voltage are: external DC trim voltage applied between the Trim input and Power Common. Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5V The output voltage range for W3 models is 0.75 to 3.3 Volts. For D12 models, the output range is 0.75 to 5 Volts. Vtrim Open 0.6835 0.670 0.650 0.630 0.583 0.530 0.4166 IMPORTANT: On W3 models only, for outputs greater than 3 Volts up to LSN2 Power Sequencing 3.3 Volts maximum, the input supply must be 4.5 Volts minimum. To retain Whereas in the old days, one master switch simultaneously turned on the proper regulation, do not exceed the 3.3V output. power for all parts of a system, many modern systems require multiple supply As with other trim adjustments, be sure to use a precision low-tempco voltages for different on-board sections. Typically the CPU or microcontroller resistor (±100 ppm/°C) mounted close to the converter with short leads. Also needs 1.8 Volts or lower. Memory (particularly DDR) may use 1.8 to 2.5 Volts. be aware that the output voltage accuracy is ±2% (typical) therefore you may Interface “glue” and “chipset” logic might use +3.3Vdc power while Input/ need to vary this resistance slightly to achieve your desired output setting. Output subsystems may need +5V. Finally, peripherals use 5V and/or 12V. Two different trim equations are used for the W3 and D12 models. +VOUT +VOUT W3 Models Resistor Trim Equation: 21070 _____________ TRIM TRIM RTRIM (W) = – 5110 VO – 0.7525 + RTRIM VTRIM – The W3 models fixed trim resistors to set the output voltage are: COMMON COMMON Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V Rtrim (kΩ) Open 80.021 41.973 23.077 15.004 6.947 3.16 Figure 6. Trim Connections www.murata-ps.com/support MDC_LSN2.D01∆  Page 9 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters Timing is Everything The first system (discrete On/Off controls) applies signals from an already- powered logic sequencer or dedicated microcontroller which turns on each This mix of system voltages is being distributed by several local power solu- downstream power section in cascaded series. This of course assumes all tions including Point-of-load (POL) DC/DC converters and sometimes a linear POL’s have On/Off controls. A distinct advantage of the sequencing controller regulator, all sourced from a master AC power supply. While this mix of volt- is that it can produce an “All On” output signal to state that the full system is ages is challenging enough, a further difficulty is the start-up and shutdown stable and ready to go to work. For additional safety, the sequencer can moni- timing relationship between these power sources and relative voltage differ- tor the output voltages of all downstream POL’s with an A/D converter system. ences between them. However the sequencer controller has some obvious difficulties besides For many systems, the CPU and memory must be powered up, boot- extra cost, wiring and programming complexity. First, power is applied as a strap loaded and stabilized before the I/O section is turned on. This avoids fast-rising, all-or-nothing step which may be unacceptable to certain circuits, uncommanded data bytes being transferred, compromising an active external especially large output bypass capacitors. These could force POL’s into network or placing the I/O section in an undefined mode. Or it keeps bad com- overcurrent shutdown. And some circuits (such as many linear regulators and mands out of disk and peripheral controllers until they are ready to go to work. some POLs) may not have convenient start-up controls. This requires design- Another goal for staggered power-up is to avoid an oversize load applied ing and fabricating external power controls such as high-current MOSFET’s. to the master source all at once. A more serious reason to manage the timing If the power up/down timing needs to be closely controlled, each POL and voltage differences is to avoid either a latchup condition in program- mable logic (a latchup might ignore commands or would respond improperly must be characterized for start-up and down times. These often vary—one POL may stabilize in 15 milliseconds whereas another takes 50 milliseconds. to them) or a high current startup situation (which may damage on-board circuits). And on the power down phase, inappropriate timing or voltages can Another problem is that the sequencing controller itself must be “already running” and stabilized before starting up other circuits. If there is a glitch in cause interface logic to send a wrong “epitaph” command. the system, the power up/down sequencer could get out of step with possible Two Approaches disastrous results. Lastly, changing the timing may require reprogramming the There are two ways to manage these timing and voltage differences. Either logic sequencer or rewriting software. the power up/down sequence can be controlled by discrete On/Off logic con- Sequence/Track Input trols for each power supply (see Figure 7). Or the power up/down cycle is set by Sequencing or Tracking circuits. Some systems combine both methods. A different power sequencing solution is employed on MPS’s LSN2 DC/DC converter. After external input power is applied and the converter stabilizes, +12Vdc a high impedance Sequence/Track input pin accepts an external analog volt- age. The output power voltage will then track this Sequence/Track input at a one-to-one ratio up to the nominal set point voltage for that converter. This “ALL ON” +VIN Sequencing input may be ramped, delayed, stepped or otherwise phased as POL +5V needed for the output power, all fully controlled by the user’s simple external A LOADS circuits. As a direct input to the converter’s feedback loop, response to the ENABLE Sequence/Track input is very fast (milliseconds). SEQUENCING CPU CONTROLLER +VIN By properly controlling this Sequence pin, most operations of the discrete +3.3V POL LOADS B On/Off logic sequencer may be duplicated. The Sequence pin system does ENABLE not use the converter’s Enable On/Off control (unless it is a master emergency shut down system). TO OTHER POLs Power Phasing Architectures Observe the simplified timing diagrams below. There are many possible power STARTUP SEQUENCE: phasing architectures and these are just some examples to help you analyze ENABLE your system. Each application will be different. Multiple output voltages may require more complex timing than that shown here. ON These diagrams illustrate the time and slew rate relationship between two OFF POL A typical power output voltages. Generally the Master will be a primary power Settling Delay voltage in the system which must be present first or coincident with any ON Slave power voltages. The Master output voltage is connected to the Slave’s OFF Sequence input, either by a voltage divider, divider-plus-capacitor or some POL B TIME Figure 7. Power Up/Down Sequencing Controller www.murata-ps.com/support MDC_LSN2.D01∆  Page 10 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters other method. Several standard sequencing architectures are prevalent. They OUTPUT VOLTAGE are concerned with three factors: ■ The time relationship between the Master and Slave voltages ■ The voltage difference relationship between the Master and Slave POL A VOUT ■ The voltage slew rate (ramp slope) of each converter’s output. POL B VOUT For most systems, the time relationship is the dominant factor. The voltage difference relationship is important for systems very concerned about possible Delayed latchup of programmable devices or overdriving ESD diodes. Lower slew VOUT Times rates avoid overcurrent shutdown during bypass cap charge-up. TIME Figure 10. Staggered or Sequential Phasing—Inclusive (Fixed Delays) OUTPUT VOLTAGE OUTPUT VOLTAGE POL A VOUT Not Drawn To Scale POL B VOUT POL A VOUT Staggered +VOUT POL B VOUT Times TIME Delayed VOUT Times Figure 8. Coincident or Simultaneous Phasing (Identical Slew Rates) TIME Figure 11. Staggered or Sequential Phasing—Exclusive (Fixed Cascaded Delays) In Figure 8, two POL’s ramp up at the same rate until they reach their dif- ferent respective final set point voltages. During the ramp, their voltages are nearly identical. This avoids problems with large currents flowing between Figures 10 and 11 show both delayed start up and delayed final voltages logic systems which are not initialized yet. Since both end voltages are differ- for two converters. Figure 10 is called “Inclusive” because the later starting ent, each converter reaches it’s setpoint voltage at a different time. POL finishes inside the earlier POL. The timing in Figure 10 is more easily built using a combined digital sequence controller and the Sequence/Track pin. OUTPUT Figure 11 is the same strategy as Figure 10 but with an “exclusive” timing VOLTAGE relationship staggered approximately the same at power-up and power-down. POL A VOUT Operation To use the Sequence pin after power start-up stabilizes, apply a rising external voltage to the Sequence input. As the voltage rises, the output voltage will POL B VOUT track the Sequence input (gain = 1). The output voltage will stop rising when it reaches the normal set point for the converter. The Sequence input may op- tionally continue to rise without any effect on the output. Keep the Sequence Coincident VOUT Times input voltage below the converter’s input supply voltage. Use a similar strategy on power down. The output voltage will stay constant TIME until the Sequence input falls below the set point. Any strategy may be used to deliver the power up/down ramps. The circuits Figure 9. Proportional or Ratiometric Phasing (Identical Vout Time) below show simple RC networks but you may also use operational amplifiers, Figure 9 shows two POLs with different slew rates in order to reach differing D/A converters, etc. final voltages at about the same time. www.murata-ps.com/support MDC_LSN2.D01∆  Page 11 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters Circuits If you wish to have a ramped power down (rather than a step down), add a small resistor in series with Q1’s drain. The circuits shown in Figures 12 through 14 introduce several concepts when using these Sequencing controls on Point-of-Load (POL) converters. These circuits are only for reference and are not intended as final designs ready for +VIN your application. Also, numerous connections are omitted for clarity. R1 MAIN +VIN SEQ/TRK POL A +VOUT = 5V RAMP RATE R1 C1 SEQ/TRK POL A +VOUT = 5V –VIN C1 –VIN R2 SEQ/TRK +VOUT = 3.3V POL B R3 C2 +VOUT = 3.3V POL B SEQ/TRK –VIN ANTI-NOISE FILTER, 1000pF TYP. Figure 14. Proportional Phasing Figure 12. Wiring for Simultaneous Phasing Figure 14 shows both a RC ramp on Master POL A and a proportional track- Figure 12 shows a basic Master (POL A) and Slave (POL B) connected so ing divider (R2 and R3) on POL B. We have also added an optional very small noise filter cap at C2. Figure 14’s circuit corresponds roughly to Figure 9’s the POL B ramps up identically to POL A as shown in timing diagram, Figure 8. RC network R1 and C1 charge up at a rate set by the R1-C1 time constant, timing for power up. giving a roughly linear ramp. As POL A reaches 3.3VOUT (the setpoint of POL Guidelines for Sequence/Track Applications B), POL B will stop rising. POL A then continues rising until it reaches 5V. R1 [1] Leave the converter’s On/Off Enable control (if installed) in the On setting. should be significantly smaller than the internal bias current resistor from the Normally, you should just leave the On/Off pin open. Sequence pin. Start with a 20kW value. We assume that the critical phase is only on power up therefore there is no provision for ramped power down. [2] Allow the converter to stabilize (typically less than 20 mS after +VIN power on) before raising the Sequence input. Also, if you wish to have a ramped power down, leave +VIN powered all during the down ramp. Do +VIN not simply shut off power. R1 [3] If you do not use the Sequence/Track pin, leave it open or tied to +VIN. SEQ/TRK POL A +VOUT = 5V [4] Observe the Output slew rate relative to the Sequence input. A rough Q1 guide is 2 Volts per millisecond maximum slew rate. If you exceed UP/DN C1 this slew rate on the Sequence pin, the converter will simply ramp up –VIN at it’s maximum output slew rate (and will not necessarily track the faster Sequence input). The reason to carefully consider the slew rate limitation is in case you want two different POL’s to precisely track Figure 13. Self-Ramping Power Up each other. Figure 13 shows a single POL and the same RC network. However, we have [5] Be aware of the input characteristics of the Sequence pin. The high added a FET at Q1 as an up/down control. When VIN power is applied to the input impedance affects the time constant of any small external ramp POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased capacitor. And the bias current will slowly charge up any external caps off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate. over time if they are not grounded. The internal pull-up resistor to +VIN is Note: Q1’s gate would typically be controlled from some external digital logic. typically 400kW to 1MW. www.murata-ps.com/support MDC_LSN2.D01∆  Page 12 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters Notice in the simplified Sequence/Track equivalent circuit (Figure 15) that Power Good Output a blocking diode effectively disconnects this circuit when the Sequence/ The Power Good Output consists of an unterminated BSS138 small signal Track pin is pulled up to +VIN or left open. field effect transistor and a dual window comparator input circuit driving the gate of the FET. Power Good is TRUE (open drain, high impedance state) if the converter’s power output voltage is within about ±10% of the setpoint. Thus, +VIN PWM the PG TRUE condition indicates that the converter is approximately within +VOUT CONTROLLER regulation. Since an overcurrent condition occurs at about 2% output voltage FEEDBACK reduction, the Power Good does not directly measure an output overcurrent 1MΩ condition at rated maximum output current. However, gross overcurrent or +VIN an output short circuit will set Power Good to FALSE (+0.2V saturation, low TRIM impedance condition). SEQ/ +LOGIC – TRK SUPPLY External Pullup IN Resistor + User’s External POWER Logic GOOD Figure 15. Sequence/Track Simplified Equivalent Schematic BSS138 HI Window [6] Allow the converter to eventually achieve its full-rated setpoint output Comparator COMMON LOGIC voltage. Do not remain in ramp up/down mode indefinitely. The converter GROUND 10mA LO POWER is characterized and meets all its specifications only at the setpoint MAX. OUTPUT voltage (plus or minus any trim voltage). During the ramp-up phase, the converter is not considered fully in regulation. This may affect perfor- HI (Open Drain) = Power OK mance with excessive high current loads at turn-on. LO (+0.2V Saturation) = Power not OK [7] The Sequence is a sensitive input into the feedback control loop of the converter. Avoid noise and long leads on this input. Keep all wiring very Figure 16. Equivalent Power Good Circuit short. Use shielding if necessary. Consider adding a small parallel ce- ramic capacitor across the Sequence/Track input (see Figure 14) to block Using a simple connection to external logic (and returned to the converter’s any external high frequency noise. Common connection), the Power Good output is unterminated so that the user may adapt the output to a variety of logic families. The PG pin may therefore [8] If one converter is slaving to another master converter, there will be a very be used with logic voltages which are not necessarily the same as the input short phase lag between the two converters. This can usually be ignored. or output power voltages. Install an external pullup resistor to the logic supply [9] You may connect two or more Sequence inputs in parallel from two voltage which is compatible with your logic system. When the Power Good is converters. Be aware of the increasing pull-up bias current and reduced out of limit, the FET is at saturation, approximately +0.2V output. Keep this input impedance. LOW (FALSE) pulldown current to less than 10mA. [10] Any external capacitance added to the converter’s output may affect Please note that Power Good is briefly false during Sequence ramp-up. ramp up/down times and ramp tracking accuracy. Ignore Power Good while in transition. www.murata-ps.com/support MDC_LSN2.D01∆  Page 13 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters MECHANICAL SPECIFICATIONS Case B11 2.00 0.32 (50.8) (8.13) Maximum 0.50 0.130 (12.7) (3.3) 10 9 B 8 7 6 A 5 4 3 2 1 0.050 0.900 0.040 (1.02) (1.27) (22.86) 0.500 0.500 (12.70) (12.70) 0.030Ø (0.76) 5 EQ. SP. @ 5 EQ. SP. @ Typical 0.100 (2.54) REAR VIEW 0.100 (2.54) Dimensions are in inches (mm shown for ref. only). 10/16 Amp Models Third Angle Projection I/O CONNECTIONS Pin Function P68 Pin Function P68 1 +Output 6 Common 2 +Output 7 +Input * Power Good output is optional. 3 +Sense In 8 +Input Tolerances (unless otherwise specified): If not installed, the pin is omitted. 4 +Output B VTRACK/Sequence .XX ± 0.02 (0.5) .XXX ± 0.010 (0.25) 5 Common 9 Trim Angles ± 2˚ A Power Good Out * 10 On/Off Control Components are shown for reference only. Case B12 1.00 0.275 6 Amp Models (25.4) (6.98) I/O CONNECTIONS Pin Function P69 1 +Output 0.50 0.130 2 VOUT Trim (12.7) (3.3) 3 Common A VTRACK/Sequence B Power Good* 4 +Input 5 4 B A 3 2 1 5 On/Off Control 0.100 0.040 (1.02) (2.54) TYP. * Power Good output is optional. REAR VIEW If not installed, the pin is omitted. 0.030Ø (0.76) 0.100 Typical 0.500 (12.7) (2.54) DIMENSIONS ARE IN INCHES (MM) www.murata-ps.com/support MDC_LSN2.D01∆  Page 14 of 15 LSN2 Series Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters Typical Performance Curves LSN2-T/6-D12 LSN2-T/6-D12 Maximum Current Temperature Derating Efficiency vs. Line Voltage and Load Current @ 25°C (VOUT = 5V) VOUT = 5V (air flow from input to output) 95 6.5 94 93 6 92 5.5 91 Natural Convection 90 5 89 100 lfm VIN = 8.3V 88 200 lfm VIN = 12V 4.5 87 400 lfm VIN = 14V 86 4 85 –40 25 30 35 40 45 50 55 60 65 70 75 80 85 1 2 3 4 5 6 Ambient Temperature ( C) ˚ Load Current (Amps) LSN2-T/6-D12 LSN2-T/6-D12 Efficiency vs. Line Voltage and Load Current @ 25°C (VOUT = 0.75V) Maximum Current Temperature Derating VOUT = 0.75V (air flow from input to output) 84 6.5 82 6 80 VIN = 8.3V 78 5.5 Natural Convection 76 5 74 100 lfm VIN = 12V 4.5 72 VIN = 14V 70 4 1 2 3 4 5 6 –40 25 30 35 40 45 50 55 60 65 70 75 80 85 Load Current (Amps) Ambient Temperature ( C) ˚ This product is subject to the following operating requirements  Murata Power Solutions, Inc. and the Life and Safety Critical Application Sales Policy:   11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. 10/22/14 Refer to: http://www.murata-ps.com/requirements/ ISO 9001 and 14001 REGISTERED Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. © 2014 Murata Power Solutions, Inc. www.murata-ps.com/support MDC_LSN2.D01∆  Page 15 of 15 Efficiency (%) Efficiency (%) Output Current (Amps) Output Current (Amps)