MURATA POWER SOLUTIONS OKDX-T/20-W12-001-C

OKDx-T/20-W12-xxx-C www.murata-ps.com 20A Digital PoL DC-DC Converter Series T Typical units ypical units FEATURES PRODUCT OVERVIEW The OKDx-T/20-W12 series are high effi ciency, standard PoL performance and safety features like  Small package: 25.65 x 13.8 x 8.2 mm (1.01 x digital point-of-Load (PoL) DC-DC power converters OVP, OCP, OTP, and UVLO, these digital converters 0.543 x 0.323 in) SIP: 26.3 x 7.6 x 15.6 mm (1.035 capable of delivering 20A/66W. Available in three have advanced features: digital current sharing (full x 0.30 x 0.614 in) different package formats, through-hole, single-in- power, no derating), non-linear transient response,  0.6 V - 3.3 V output voltage range line, and surface mount, these converters have a optimized dead time control, synchronization, and  High effi ciency, typ. 97.1% at 5Vin, 3.3Vout half load typical effi ciency of 97.1%. PMBus™ compatibility phase spreading. These converters are ideal for use allows monitoring and confi guration of critical in telecommunications, networking, and distributed  Confi guration and Monitoring via PMBus™ system-level performance requirements. Apart from power applications.  Synchonization & phase spreading  Current sharing, Voltage Tracking & Voltage Power Management via PMBus™ Applications margining   Confi gurable soft-start/stop Distributed power architectures  MTBF 20.2 Mh   Confi gurable output voltage (Vout) and voltage Intermediate bus voltage applications  Non-Linear Response for reduction of decou- margins (Margin low and Margin high)  Servers and storage applications pling capacitor  Confi gurable protection limits for OVP, input over  Network equipment  Remote control & power good voltage, input under voltage, over current, on/off,  and temperature Output short-circuit, output over voltage, & over temperature protection  Status monitor Vout, Iout, Vin, Temp, Power  Certifi ed to UL/IEC 60950-1 good, and On/Off PART NUMBER STRUCTURE OKD x - T / 20 - W12 - xxx - C Digital Non-isolated PoL RoHS Hazardous Substance Compliance C = RoHS-6 (does not claim EU RoHS exemption Y = Surface Mount 7b – lead in solder) H = Horizontal Mount Through-Hole X = SIP Trimmable Output Software Confi guration Digits Voltage Range (001 is positive turn-on logic) 0.6 - 3.3Vdc (002 is negative turn-on logic)* *Special quantity order is required; Maximum Rated Output contact Murata Power Solutions for Input Voltage Range Current in Amps MOQ and lead times. 4.5-14Vdc PM www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 1 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series ORDERING GUIDE Model Number Output OKDY-T/20-W12-001-C OKDH-T/20-W12-001-C 0.6-3.3 V, 20 A/ 66 W OKDX-T/20-W12-001-C Absolute Maximum Ratings Characteristics Min Typ Max Unit TP1, TP2 Operating temperature (see Thermal Consideration section) -40 125 °C TS Storage temperature -40 125 °C VI Input voltage (See Operating Information Section for input and output voltage relations) -0.3 16 V Logic I/O voltage CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, GCB, PG -0.3 6.5 V Ground voltage differential -S, PREF, GND -0.3 0.3 V Analog pin voltage VO, +S, VTRK -0.3 6.5 V General and Safety Conditions Min Typ Max Unit Safety Designed for UL/IEC/EN 60950 1 Calculated MTBF Telcordia SR-332, Issue 2 Method 1 20.2 Mhrs Stress in excess of Absolute Maximum Ratings may cause permanent tionality and performance with the default confi guration fi le, unless otherwise damage. Absolute Maximum Ratings, sometimes referred to as no destruction specifi ed. The default confi guration fi le is designed to fi t most application limits, are normally tested with one parameter at a time exceeding the limits needs with focus on high effi ciency. If different characteristics are required it in the Electrical Specifi cation. If exposed to stress above these limits, function is possible to change the confi guration fi le to optimize certain performance and performance may degrade in an unspecifi ed manner. characteristics. Note that current sharing operation requires changed confi gu- ration fi le. Confi guration File In this Technical specifi cation examples are included to show the possibili- This product is designed with a digital control circuit. The control circuit uses ties with digital control. See Operating Information section for information a confi guration fi le which determines the functionality and performance of the about trade offs when optimizing certain key performance characteristics. product. The Electrical Specifi cation table shows parameter values of func- VIN VOUT C C I O GND +Sense -Sense (PGOOD) (SA1) CTRL SALERT VSET SYNC Controller and digital interface SDA SCL SA0 GCB PREF VTRK Fundamental Circuit Diagram www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 2 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Electrical Specifi cations, OKDY-T/20-W12-xxx-C and OKDH-T/20-W12-xxx-C TP1 = -30 to +95°C, VIN = 4.5 to 14 V, VIN > VOUT + 1.0 V Typical values given at: TP1 = +25 °C, VIN = 12.0 V, max IOUT, unless otherwise specifi ed under Conditions. Default confi guration fi le, 190 10-CDA 102 0206/001. External CIN = 470 μF/10 mΩ, COUT = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics Conditions Min Typ Max Unit V Input voltage rise time monotonic 2.4 V/ms I Output voltage without pin strap 1.2 V Output voltage adjustment range 0.60 3.3 V Output voltage adjustment including margining See Note 17 0.54 3.63 V Output voltage set-point resolution ±0.025% Vo Including line, load, temp. -1 1 % See Note 14 Output voltage accuracy Current sharing operation -2 2 % See Note 15 V Internal resistance +S/-S to VOUT/GND 4.7 Ω O V = 0.6 V 2 O V = 1.0 V 2 O Line regulation mV V = 1.8 V 2 O V = 3.3 V 3 O V = 0.6 V 3 O V = 1.0 V 2 O Load regulation; I = 0 - 100% mV O V = 1.8 V 2 O V = 3.3 V 2 O V = 0.6 V 20 O V = 1.0 V 30 Output ripple & noise O V mVp-p Oac C = 470 μF (minimum external capacitance). See Note 11 V = 1.8 V 40 O O V = 3.3 V 60 O I Output current See Note 18 0.001 20 A O V = 0.6 V 1.26 O V = 1.0 V 1.94 O I Static input current at max I A S O V = 1.8 V 3.31 O V = 3.3 V 5.89 O I Current limit threshold 22 30 A lim V = 0.6 V 8 O V = 1.0 V 6 O I Short circuit current RMS, hiccup mode, See Note 3 A sc V = 1.8 V 5 O V = 3.3 V 4 O V = 0.6 V 84.0 O V = 1.0 V 89.3 O 50% of max I % O V = 1.8 V 92.8 O V = 3.3 V 94.8 O  Effi ciency V = 0.6 V 79.3 O V = 1.0 V 86.0 O max I % O V = 1.8 V 90.7 O V = 3.3 V 93.6 O V = 0.6 V 3.12 O V = 1.0 V 3.25 O P Power dissipation at max I W d O V = 1.8 V 3.68 O V = 3.3 V 4.52 O V = 0.6 V 0.56 O Input idling power Default confi guration: Continues V = 1.0 V 0.57 O P W li (no load) Conduction Mode, CCM V = 1.8 V 0.68 O V = 3.3 V 0.99 O Default confi guration: Turned off with mW P Input standby power Monitoring enabled, 180 CTRL CTRL-pin Precise timing enabled C Internal input capacitance 70 μF i www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 3 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit C Internal output capacitance200 μF o Total external output capacitance See Note 9 300 15 000 μF C ESR range of capacitors OUT See Note 9 5 30 mΩ (per single capacitor) V = 0.6 V 85 O Load transient peak Default confi guration voltage deviation V = 1.0 V 85 O di/dt = 2 A/μs V (H to L) mV tr1 C = 470 μF (minimum external O V = 1.8 V 90 Load step 25-75-25% O capacitance) see Note 12 of max I O V = 3.3 V 135 O V = 0.6 V 80 O Load transient recovery Default confi guration time, Note 5 V = 1.0 V 90 O di/dt = 2 A/μs t (H to L) μs tr1 C = 470 μF (minimum external O V = 1.8 V 100 Load step 25-75-25% O capacitance) see Note 12 of max I O V = 3.3 V 100 O Switching frequency 320 kHz f Switching frequency range PMBus™ confi gurable 200-640 kHz s Switching frequency set-point accuracy -5 5 % Control Circuit PWM Duty Cycle 5 95 % Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source -13 13 % UVLO threshold 3.85 V UVLO threshold range PMBus™ confi gurable 3.85-14 V Set point accuracy -150 150 mV Input Under Voltage Lockout, UVLO hysteresis 0.35 V UVLO UVLO hysteresis range PMBus™ confi gurable 0-10.15 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms IOVP threshold 16 V IOVP threshold range PMBus™ confi gurable 4.2-16 V Set point accuracy -150 150 mV Input Over Voltage Protection, IOVP hysteresis 1 V IOVP IOVP hysteresis range PMBus™ confi gurable 0-11.8 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms PG threshold 90 % V O Power Good, PG, PG hysteresis 5% V O See Note 2 PG delay 10 ms PG delay range PMBus™ confi gurable 0-500 s UVP threshold 85 % V O UVP threshold range PMBus™ confi gurable 0-100 % V O UVP hysteresis 5% V O Output voltage OVP threshold 115 % V O Over/Under Voltage Protection, OVP threshold range PMBus™ confi gurable 100-115 % V O OVP/UVP UVP/OVP response time25 μs UVP/OVP PMBus™ confi gurable 5-60 μs response time range Fault response See Note 3 Automatic restart, 70 ms OCP threshold 26 A OCP threshold range PMBus™ confi gurable 0-26 A Over Current Protection, Protection delay, See Note 4 32 T sw OCP Protection delay range PMBus™ confi gurable 1-32 T sw Fault response See Note 3 Automatic restart, 70 ms OTP threshold 120 C Over Temperature Protection, OTP threshold range PMBus™ confi gurable -40…+120 C OTP at P1 OTP hysteresis 15 C See Note 8 OTP hysteresis range PMBus™ confi gurable 0-160 C Fault response See Note 3 Automatic restart, 240 ms www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 4 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit V Logic input low threshold SYNC, SA0, SA1, SCL, SDA, GCB, CTRL, 0.8 V IL V Logic input high threshold VSET 2 V IH I Logic input low sink current CTRL 0.6 mA IL V Logic output low signal level 0.4 V OL V Logic output high signal level 2.25 V OH SYNC, SCL, SDA, SALERT, GCB, PG I Logic output low sink current 4mA OL I Logic output high source current 2mA OH t Setup time, SMBus See Note 1 300 ns set t Hold time, SMBus See Note 1 250 ns hold t Bus free time, SMBus See Note 1 2 ms free C Internal capacitance on logic pins 10 pF p Initialization time See Note 10 35 ms Delay duration See Note 16 10 ms Delay duration range PMBus™ confi gurable 2-500000 Default confi guration: CTRL controlled ±0.25 ms Output Voltage Delay accuracy Precise timing enabled Delay Time turn-on PMBus™ controlled See Note 6 Precise timing disabled -0.25/+4 ms Current sharing operation Delay accuracy -0.25/+4 ms turn-off Ramp duration 10 Output Voltage ms Ramp duration range PMBus™ confi gurable 0-200 Ramp Time 100 μs See Note 13 Ramp time accuracy Current sharing operation 20 % VTRK Input Bias Current V = 5.5 V 110 200 μA VTRK 100% tracking, see Note 7 -100 100 mV Current sharing operation VTRK Tracking Ramp Accuracy (V - V ) O VTRK 2 phases, 100% tracking ±100 mV V = 1.0 V, 10 ms ramp O 100% Tracking -1 1 % VTRK Regulation Accuracy (V - V ) Current sharing operation O VTRK -2 2 % 100% Tracking Steady state operation Max 2 x READ_IOUT monitoring accuracy Current difference between products in a current sharing group Ramp-up 2 A Number of products in a current sharing group 7 READ_VIN vs V3 % I READ_VOUT vs V 1% O I =0-20 A, T = 0 to +95 °C O P1 Monitoring accuracy READ_IOUT vs I ±1.4 A O V = 4.5-14 V, V = 1.0 V I O I =0-20 A, T = 0 to +95 °C O P1 READ_IOUT vs I ±2.6 A O V = 4.5-14 V, V = 0.6-3.3 V I O 2 Note 1: See section I C/SMBus Setup and Hold Times – Defi nitions. Note 10: See section Initialization Procedure. Note 2: Monitorable over PMBus™ Interface. Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. fault reappear after restart. See Operating Information and AN302 for other fault response options. Note 13: Time for reaching 100% of nominal Vout. Note 4: Tsw is the switching period. Note 14: For Vout < 1.0 V accuracy is ±10 mV. For further deviations see section Output Voltage Adjust using PMBus™. Note 5: Within ±3% of VO Note 15: Accuracy here means deviation from ideal output voltage level given by confi gured droop and actual load. Note 6: See section Soft-start Power Up. Includes line, load and temperature variations. Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals Note 16: For current sharing the Output Voltage Delay Time must be reconfi gured to minimum 15 ms. accuracy will depend on the regulator bandwidth. Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative. Note 8: See section Over Temperature Protection (OTP). Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). Note 9: See section External Capacitors. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 5 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Efficiency and Power Dissipation Efficiency vs. Output Current, V = 5 V Power Dissipation vs. Output Current, V = 5 V I I [%] [W] 100 5 4 95 90 3 0,6 V 0,6 V 85 2 1,0 V 1,0 V 1,8 V 1,8 V 80 1 3,3 V 3,3 V 75 0 04 8 12 16 20[A] 048 12 16 20[A] Efficiency vs. load current and output voltage: Dissipated power vs. load current and output voltage: T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current, V = 12 V Power Dissipation vs. Output Current, V =12V I I [%] [W] 100 5 95 4 90 3 0,6 V 0,6 V 85 2 1,0 V 1,0 V 1,8 V 1,8 V 80 1 3,3 V 3,3 V 75 0 04 8 12 16 20[A] 0 4 8 12 16 20 [A] Efficiency vs. load current and output voltage at Dissipated power vs. load current and output voltage: T = +25 °C, V =12 V, f =320 kHz, C =470 μF/10 mŸ. T = +25 °C, V =12 V, f =320 kHz, C =470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current and Power Dissipation vs. Output Current and Switching Frequency Switching frequency [%] [W] 5 95 200 200 kHz 4 90 kHz 320 320 3 85 kHz kHz 480 480 2 80 kHz kHz 640 640 1 75 kHz kHz 0 70 04 8 12 16 20[A] 0 4 8 121620[A] Efficiency vs. load current and switch frequency at Dissipated power vs. load current and switch frequency at T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ P1 I O O P1 I O O Default configuration except changed frequency Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 6 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Load Transient Load Transient vs. External Capacitance, V = 1.0 V Load Transient vs. External Capacitance, V = 3.3 V O O [mV] [mV] 200 200 Default Default PID/NLR 160 PID/NLR 150 Opt. PID, Opt. PID, 120 No NLR No NLR 100 Default PID, Default PID, 80 Opt. NLR Opt. NLR 50 Opt. Opt. 40 PID/NLR PID/NLR 0 0 012 345 012345[mF] [mF] Load transient peak voltage deviation vs. external capacitance. Load transient peak voltage deviation vs. external capacitance. Step-change (5-15-5 A). Parallel coupling of capacitors with 470 μF/10 Pȍ, Step-change (5-15-5 A). Parallel coupling of capacitors with 470 μF/10 Pȍ, T = +25 °C, V =12 V, V = 1.0 V, f = 320 kHz, di/dt = 2 A/μs T = +25 °C, V =12 V, V = 3.3 V, f = 320 kHz, di/dt = 2 A/μs P1 I O sw P1 I O sw Load transient vs. Switch Frequency Output Load Transient Response, Default PID/NLR [mV] 240 Default 200 PID/NLR Opt. PID, No 160 NLR 120 Default PID, Opt. NLR 80 Opt. PID/NLR 40 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Output voltage response to load current Top trace: output voltage (200 Step-change (5-15-5 A). step-change (5-15-5 A) at: mV/div.). T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: load current (5 P1 I O O P1 I O di/dt = 2 A/μs, f = 320 kHz, A/div.). sw C =470 μF/10 mŸ Time scale: (0.1 ms/div.). O www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 7 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Output Current Characteristic Output Current Derating, V = 0.6 V Output Current Derating, V = 1.0 V O O [A] [A] 25 25 3.0 m/s 3.0 m/s 20 20 2.0 m/s 2.0 m/s 15 1.0 m/s 15 1.0 m/s 0.5 m/s 0.5 m/s 10 10 Nat. Conv. Nat. Conv. 5 5 0 0 60 70 80 90 100 110 120 60 70 80 90 100 110 120 [°C] [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 0.6 V, V = 12 V. See Thermal Consideration section. V = 1.0 V, V = 12 V. See Thermal Consideration section. O I O I Output Current Derating, V = 1.8 V Output Current Derating, V =3.3 V O O [A] [A] 25 25 3.0 m/s 3.0 m/s 20 20 2.0 m/s 2.0 m/s 15 1.0 m/s 15 1.0 m/s 0.5 m/s 10 0.5 m/s 10 Nat. Conv. Nat. Conv. 5 5 0 0 60 70 80 90 100 110 120 60 70 80 90 100 110 120 [°C] [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 1.8 V, V = 12 V. See Thermal Consideration section. V = 3.3 V, V = 12 V. See Thermal Consideration section. O I O I Current Limit Characteristics, V = 1.0 V Current Limit Characteristics, V = 3.3 V O O [V] [V] 1,2 4,0 1,0 3,0 0,8 4.5 V 4.5 V 5.0 V 5.0 V 0,6 2,0 12 V 12 V 0,4 14 V 14 V 1,0 0,2 0,0 0,0 20 22 24 26 28 30 20 22 24 26 28 30 [A] [A] Output voltage vs. load current at T = +25 °C, V = 1.0 V. Output voltage vs. load current at T = +25 °C, V = 3.3 V. P1 O P1 O Note: Output enters hiccup mode at current limit. Output enters hiccup mode at current limit. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 8 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Output Voltage Output Ripple & Noise, V = 1.0 V Output Ripple & Noise, V =3.3 V O O Output voltage ripple at: T = +25 °C, Trace: output voltage (20 mV/div.). Output voltage ripple at: T = +25 °C, Trace: output voltage (20 mV/div.). P1 P1 V = 12 V, C =4 70 μF/10 mŸ Time scale: (2 μs/div.). V = 12 V, C = 470 μF/10 mŸ Time scale: (2 μs/div.). I O I O I =20A I =20 A O O Output Ripple vs. Input Voltage Output Ripple vs. Frequency [mV ] [mV ] pk-pk pk-pk 70 80 70 60 60 50 0.6 V 0.6 V 50 40 1.0 V 1.0 V 40 1.8 V 30 1.8 V 30 3.3 V 3.3 V 20 20 10 10 0 0 [V] [kHz] 579 11 13 200 300 400 500 600 Output voltage ripple V at: T = +25 °C, C = 470μF/10 mŸ, I = 20 A Output voltage ripple V at: T = +25 °C, V = 12 V, C = 470 μF/10 mŸ, pk-pk P1 O O pk-pk P1 I O I = 20 A. Default configuration except changed frequency. O Output Ripple vs. External Capacitance Load regulation, V =1.0 V O [mV] [V] 60 1,010 50 1,005 0.6V 40 4.5 V 1.0 V 5.0 V 30 1,000 12 V 1.8 V 20 14 V 3.3 V 0,995 10 0 0,990 0 4 8 12 16 20 012 345 [A] [mF] Output voltage ripple V at: T = +25 °C, V = 12 V, I =20A. Load regulation at V = 1.0 V, T = +25 °C, C =470 μF/10 mŸ pk-pk P1 I O o P1 O Parallel coupling of capacitors with 470 μF/10 mȍ, www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 9 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Start-up and shut-down Start-up by input source Shut-down by input source Start-up enabled by connecting V at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div.). I T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: input voltage (5 V/div.). V at: Bottom trace: input voltage (5 V/div.). P1 I O I CO = 470 μF/10 mŸ, IO =20 A Time scale: (20 ms/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (2 ms/div.). C = 470 μF/10 mŸ, I =20 A O O Start-up by CTRL signal Shut-down by CTRL signal Start-up by enabling CTRL signal at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: CTRL signal (5 V/div.). V at: Bottom trace: CTRL signal (5 V/div.). P1 I O I C = 470 μF/10 mŸ, I =20 A Time scale: (20 ms/div.). T = +25 °C, V = 12 V, V = 1.0 V Time scale: (2 ms/div.). O O P1 I O C = 470 μF/10 mŸ, I =20 A O O www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 10 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Electrical Specifi cations, OKDX-T/20-W12-xxx-C T = -30 to +95 °C, V = 4.5 to 14 V, V > V + 1.0 V P1 I I O Typical values given at: T = +25 °C, V = 12.0 V, max I , unless otherwise specifi ed under Conditions. P1 I O Default confi guration fi le, 190 10-CDA 102 0259/001. External C = 470 μF/10 mΩ, C = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types. IN OUT Sense pins are connected to the output pins. Characteristics Conditions Min Typ Max Unit V Input voltage rise time monotonic 2.4 V/ms I Output voltage without pin strap 1.2 V Output voltage adjustment range 0.60 3.3 V Output voltage adjustment including margining See Note 17 0.54 3.63 V Output voltage set-point resolution ±0.025 % Vo Including line, load, temp. -1 1 % See Note 14 Output voltage accuracy Current sharing operation -2 2 % See Note 15 V Internal resistance +S/-S to VOUT/GND 4.7 Ω O V = 0.6 V 2 O V = 1.0 V 2 O mV Line regulation V = 1.8 V 3 O V = 3.3 V 3 O V = 0.6 V 3 O V = 1.0 V 2 O Load regulation; I = 0 - 100% mV O V = 1.8 V 2 O V = 3.3 V 2 O V = 0.6 V 20 O Output ripple & noise V = 1.0 V 30 O V mVp-p Oac C = 470 μF (minimum external capacitance). See Note 11 V = 1.8 V 40 O O V = 3.3 V 60 O I Output current See Note 18 0.001 20 A O V = 0.6 V 1.29 O V = 1.0 V 1.97 O I Static input current at max I A S O V = 1.8 V 3.34 O V = 3.3 V 5.92 O I Current limit threshold 22 30 A lim V = 0.6 V 8 O V = 1.0 V 6 O I Short circuit current RMS, hiccup mode, See Note 3 A sc V = 1.8 V 5 O V = 3.3 V 4 O V = 0.6 V 83.5 O V = 1.0 V 89.0 O 50% of max I % O V = 1.8 V 92.7 O V = 3.3 V 94.8 O � Effi ciency V = 0.6 V 78.0 O V = 1.0 V 85.3 O max I % O V = 1.8 V 90.4 O V = 3.3 V 93.5 O V = 0.6 V 3.40 O V = 1.0 V 3.45 O P Power dissipation at max I W d O V = 1.8 V 3.86 O V = 3.3 V 4.62 O V = 0.6 V 0.56 O Input idling power Default confi guration: Continues V = 1.0 V 0.57 O P W li (no load) Conduction Mode, CCM V = 1.8 V 0.69 O V = 3.3 V 1.00 O Default confi guration: Turned off with mW P Input standby power Monitoring enabled, 180 CTRL CTRL-pin Precise timing enabled C Internal input capacitance 70 μF i C Internal output capacitance 200 μF o www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 11 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit Total external output capacitance See Note 9 300 15 000 μF C ESR range of capacitors OUT See Note 9 5 30 mΩ (per single capacitor) V = 0.6 V 75 O Load transient peak Default confi guration voltage deviation V = 1.0 V 80 O di/dt = 2 A/μs V (H to L) mV tr1 C = 470 μF (minimum external O V = 1.8 V 105 Load step 25-75-25% O capacitance) see Note 12 of max I O V = 3.3 V 120 O V = 0.6 V 40 O Load transient recovery Default confi guration time, Note 5 V = 1.0 V 50 O di/dt = 2 A/μs t (H to L) μs tr1 C = 470 μF (minimum external O V = 1.8 V 100 Load step 25-75-25% O capacitance) see Note 12 of max I O V = 3.3 V 100 O Switching frequency 320 kHz f Switching frequency range PMBus™ confi gurable 200-640 kHz s Switching frequency set-point accuracy -5 5 % Control Circuit PWM Duty Cycle 5 95 % Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source -13 13 % UVLO threshold 3.85 V UVLO threshold range PMBus™ confi gurable 3.85-14 V Set point accuracy -150 150 mV Input Under Voltage Lockout, UVLO hysteresis 0.35 V UVLO UVLO hysteresis range PMBus™ confi gurable 0-10.15 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms IOVP threshold 16 V IOVP threshold range PMBus™ confi gurable 4.2-16 V Set point accuracy -150 150 mV Input Over Voltage Protection, IOVP hysteresis 1 V IOVP IOVP hysteresis range PMBus™ confi gurable 0-11.8 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms PG threshold 90 % V O Power Good, PG, PG hysteresis 5% V O See Note 2 PG delay 10 ms PG delay range PMBus™ confi gurable 0-500 s UVP threshold 85 % V O UVP threshold range PMBus™ confi gurable 0-100 % V O UVP hysteresis 5% V O Output voltage OVP threshold 115 % V O Over/Under Voltage Protection, OVP threshold range PMBus™ confi gurable 100-115 % V O OVP/UVP UVP/OVP response time 25 μs UVP/OVP PMBus™ confi gurable 5-60 μs response time range Fault response See Note 3 Automatic restart, 70 ms OCP threshold 26 A OCP threshold range PMBus™ confi gurable 0-26 A Over Current Protection, Protection delay, See Note 4 5 T sw OCP Protection delay range PMBus™ confi gurable 1-32 T sw Fault response See Note 3 Automatic restart, 70 ms OTP threshold 120 C OTP threshold range PMBus™ confi gurable -40…+120 C Over Temperature Protection, OTP at P1 OTP hysteresis 15 C See Note 8 OTP hysteresis range PMBus™ confi gurable 0-160 C Fault response See Note 3 Automatic restart, 240 ms www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 12 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit V Logic input low threshold SYNC, SA0, SA1, SCL, SDA, GCB, CTRL, 0.8 V IL V Logic input high threshold VSET 2 V IH I Logic input low sink current CTRL 0.6 mA IL V Logic output low signal level 0.4 V OL V Logic output high signal level 2.25 V OH SYNC, SCL, SDA, SALERT, GCB, PG I Logic output low sink current 4mA OL I Logic output high source current 2mA OH t Setup time, SMBus See Note 1 300 ns set t Hold time, SMBus See Note 1 250 ns hold t Bus free time, SMBus See Note 1 2 ms free C Internal capacitance on logic pins 10 pF p Initialization time See Note 10 35 ms Delay duration See Note 16 10 ms Delay duration range PMBus™ confi gurable 2-500000 Default confi guration: CTRL controlled ±0.25 ms Output Voltage Delay accuracy Precise timing enabled Delay Time turn-on PMBus™ controlled See Note 6 Precise timing disabled -0.25/+4 ms Current sharing operation Delay accuracy -0.25/+4 ms turn-off Ramp duration 10 Output Voltage ms Ramp duration range PMBus™ confi gurable 0-200 Ramp Time 100 μs See Note 13 Ramp time accuracy Current sharing operation 20 % VTRK Input Bias Current V = 5.5 V 110 200 μA VTRK 100% tracking, see Note 7 -100 100 mV Current sharing operation VTRK Tracking Ramp Accuracy (V - V ) O VTRK 2 phases, 100% tracking ±100 mV V = 1.0 V, 10 ms ramp O 100% Tracking -1 1 % VTRK Regulation Accuracy (V - V ) Current sharing operation O VTRK -2 2 % 100% Tracking Steady state operation Max 2 x READ_IOUT monitoring accuracy Current difference between products in a current sharing group Ramp-up 2 A Number of products in a current sharing group 7 READ_VIN vs V 3% I READ_VOUT vs V 1% O I =0-20 A, T = 0 to +95 °C O P1 Monitoring accuracy READ_IOUT vs I ±1.4 A O V = 4.5-14 V, V = 1.0 V I O I =0-20 A, T = 0 to +95 °C O P1 READ_IOUT vs I ±2.6 A O V = 4.5-14 V, V = 0.6-3.3 V I O 2 Note 1: See section I C/SMBus Setup and Hold Times – Defi nitions. Note 10: See section Initialization Procedure. Note 2: Monitorable over PMBus™ Interface. Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. fault reappear after restart. See Operating Information and AN302 for other fault response options. Note 13: Time for reaching 100% of nominal Vout. Note 4: Tsw is the switching period. Note 14: For Vout < 1.0 V accuracy is ±10 mV. For further deviations see section Output Voltage Adjust using PMBus™. Note 5: Within ±3% of VO Note 15: Accuracy here means deviation from ideal output voltage level given by confi gured droop and actual load. Note 6: See section Soft-start Power Up. Includes line, load and temperature variations. Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals Note 16: For current sharing the Output Voltage Delay Time must be reconfi gured to minimum 15 ms. accuracy will depend on the regulator bandwidth. Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative. Note 8: See section Over Temperature Protection (OTP). Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). Note 9: See section External Capacitors. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 13 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Efficiency and Power Dissipation Efficiency vs. Output Current, V = 5 V Power Dissipation vs. Output Current, V = 5 V I I [%] [W] 100 5 95 4 90 3 0,6 V 0,6 V 85 2 1,0 V 1,0 V 1,8 V 1,8 V 80 1 3,3 V 3,3 V 75 0 0 4 8 121620[A] 0 4 8 12 16 20 [A] Efficiency vs. load current and output voltage: Dissipated power vs. load current and output voltage: T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current, V = 12 V Power Dissipation vs. Output Current, V = 12 V I I [%] [W] 100 5 95 4 90 3 0,6 V 0,6 V 85 2 1,0 V 1,0 V 1,8 V 1,8 V 1 80 3,3 V 3,3 V 75 0 0 4 8 12 16 20 [A] 0 4 8 121620[A] Efficiency vs. load current and output voltage at Dissipated power vs. load current and output voltage: T = +25 °C, V =12 V, f =320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V =12 V, f =320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current and Power Dissipation vs. Output Current and Switching Frequency Switching frequency [%] [W] 5 95 200 200 kHz 4 90 kHz 320 320 3 85 kHz kHz 480 480 80 2 kHz kHz 640 640 75 1 kHz kHz 70 0 0 4 8 121620[A] 04 8 12 16 20[A] Efficiency vs. load current and switch frequency at Dissipated power vs. load current and switch frequency at T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ P1 I O O P1 I O O Default configuration except changed frequency Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 14 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Load Transient Load Transient vs. External Capacitance, V = 1.0 V Load Transient vs. External Capacitance, V = 3.3 V O O [mV] [mV] 160 160 Default Default PID/NLR PID/NLR 120 120 Opt. PID, Opt. PID, No NLR No NLR 80 80 Default PID, Default PID, Opt. NLR Opt. NLR 40 40 Opt. Opt. PID/NLR PID/NLR 0 0 012 345 [mF] 012345[mF] Load transient peak voltage deviation vs. external capacitance. Load transient peak voltage deviation vs. external capacitance. Step-change (5-15-5 A). Parallel coupling of capacitors with 470 μF/10 Pȍ, Step-change (5-15-5 A). Parallel coupling of capacitors with 470 μF/10 Pȍ, T = +25 °C, V =12 V, V =1.0 V, f = 320 kHz, di/dt = 2 A/μs T = +25 °C, V =12 V, V = 3.3 V, f = 320 kHz, di/dt = 2 A/μs P1 I O sw P1 I O sw Load transient vs. Switch Frequency Output Load Transient Response, Default PID/NLR [mV] 160 Default PID/NLR 120 Opt. PID, No NLR 80 Default PID, Opt. NLR Opt. 40 PID/NLR 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Output voltage response to load Top trace: output voltage (200 mV/div.). Step-change (5-15-5 A). current step-change (5-15-5 A) at: Bottom trace: load current (5 A/div.). T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ T = +25 °C, V = 12 V, V = 1.0 V Time scale: (0.1 ms/div.). P1 I O O P1 I O di/dt = 2 A/μs, f = 320 kHz sw C = 470 μF/10 mŸ O www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 15 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Output Current Characteristic Output Current Derating, V = 0.6 V Output Current Derating, V = 1.0 V O O [A] [A] 25 25 3.0 m/s 3.0 m/s 20 20 2.0 m/s 2.0 m/s 15 15 1.0 m/s 1.0 m/s 0.5 m/s 0.5 m/s 10 10 Nat. Conv. Nat. Conv. 5 5 0 0 60 70 80 90 100 110 120 [°C] 60 70 80 90 100 110 120 [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 0.6 V, V = 12 V. See Thermal Consideration section. V = 1.0 V, V = 12 V. See Thermal Consideration section. O I O I Output Current Derating, V = 1.8 V Output Current Derating, V =3.3 V O O [A] [A] 25 25 3.0 m/s 3.0 m/s 20 20 2.0 m/s 2.0 m/s 15 15 1.0 m/s 1.0 m/s 0.5 m/s 0.5 m/s 10 10 Nat. Conv. Nat. Conv. 5 5 0 0 60 70 80 90 100 110 120 [°C] 60 70 80 90 100 110 120 [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 1.8 V, V = 12 V. See Thermal Consideration section. V = 3.3 V, V = 12 V. See Thermal Consideration section. O I O I Current Limit Characteristics, V = 1.0 V Current Limit Characteristics, V = 3.3 V O O [V] [V] 1,2 4,0 1,0 3,0 4.5 V 0,8 4.5 V 5.0 V 5.0 V 2,0 0,6 12 V 12 V 14 V 0,4 14 V 1,0 0,2 0,0 0,0 20 22 24 26 28 30 [A] 20 22 24 26 28 30 [A] Output voltage vs. load current at T = +25 °C, V = 1.0 V Output voltage vs. load current at T = +25 °C, V = 3.3 V. P1 O P1 O Note: Output enters hiccup mode at current limit. Note: Output enters hiccup mode at current limit. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 16 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Output Voltage Output Ripple & Noise, V = 1.0 V Output Ripple & Noise, V = 3.3 V O O Output voltage ripple at: T = +25 °C, Trace: output voltage (10 mV/div.). Output voltage ripple at: T = +25 °C, Trace: output voltage (10 mV/div.). P1 P1 V = 12 V, C = 470μF/10 mŸ Time scale: (2 μs/div.). V = 12 V, C = 470 μF/10 mŸ Time scale: (2 μs/div.). I O I O I = 20 A I = 20 A O O Output Ripple vs. Input Voltage Output Ripple vs. Frequency [mV ] pk-pk [mV ] pk-pk 60 70 60 50 0.6 V 50 0.6 V 40 1.0 V 40 1.0 V 30 1.8 V 1.8 V 30 3.3 V 20 3.3 V 20 10 10 0 0 [kHz] [V] 200 300 400 500 600 57 9 11 13 Output voltage ripple V at: T = +25 °C, C = 470 μF/10 mŸ, I = 20 A. Output voltage ripple V at: T = +25 °C, V = 12 V, C = 470 μF/10 mŸ, pk-pk P1 O O pk-pk P1 I O IO = 20 A. Default configuration except changed frequency. Output Ripple vs. External Capacitance Load regulation, V =1.0V O [V] [mV] 60 1,010 50 1,005 0.6V 40 4.5 V 1.0 V 5.0 V 30 1,000 1.8 V 12 V 20 14 V 3.3 V 0,995 10 0 0,990 012 345 [mF] 048 12 16 20 [A] Output voltage ripple V at: T = +25 °C, V = 12 V, I = 20 A. Load regulation at V =1.0 V, T = +25 °C, C = 470 μF/10 mŸ pk-pk P1 I O o P1 O Parallel coupling of capacitors with 470 μF/10 mȍ, www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 17 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Characteristics Start-up and shut-down Start-up by input source Shut-down by input source Start-up enabled by connecting V at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). I T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: input voltage (5 V/div.). V at: Bottom trace: input voltage (5 V/div.). P1 I O I CO = 470 μF/10 mŸ, IO =20 A Time scale: (20 ms/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (2 ms/div.). C = 470 μF/10 mŸ, I =20 A O O Start-up by CTRL signal Shut-down by CTRL signal Start-up by enabling CTRL signal at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting V Top trace: output voltage (0.5 V/div). I T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: CTRL signal (5 V/div.). at: Bottom trace: CTRL signal (5 V/div.). P1 I O C = 470 μF/10 mŸ, I =20 A Time scale: (20 ms/div.). T = +25 °C, V = 12 V, V = 1.0 V Time scale: (2 ms/div.). O O P1 I O C = 470 μF/10 mŸ, I =20 A O O www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 18 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series EMC Specifi cation Output Ripple and Noise Conducted EMI measured according to test set-up below. The fundamental Output ripple and noise is measured according to fi gure below. switching frequency is 320 kHz at VI = 12 V, max IO. A 50 mm conductor works as a small inductor forming together with the two capacitors as a damped fi lter. Conducted EMI Input terminal value (typical for default confi guration) 50 mm conductor Vout Tantalum Ceramic Capacitor Capacitor +S Output 10 μF 0.1 μF Capacitor 470 μF/10 m Ω –S GND 50 mm conductor BNC-contact to oscilloscope Output ripple and noise test set-up. Operating information Power Management Overview This product is equipped with a PMBus™ interface. The product incorporates EMI without fi lter a wide range of readable and confi gurable power management features that are simple to implement with a minimum of external components. Addition- To spectrum ally, the product includes protection features that continuously safeguard the analyzer load from damage due to unexpected system faults. A fault is also shown as an alert on the SALERT pin. The following product parameters can continu- ously be monitored by a host: Input voltage, output voltage/current, and RF Current probe internal temperature. If the monitoring is not needed it can be disabled and 1kHz – 50MHz Resistive Battery the product enters a low power mode reducing the power consumption. The load supply protection features are not affected. The product is delivered with a default confi guration suitable for a wide C1 POL range operation in terms of input voltage, output voltage, and load. The confi guration is stored in an internal Non-Volatile Memory (NVM). All power management functions can be reconfi gured using the PMBus™ interface. Please contact your local Murata Power Solutions representative for design 50mm support of custom confi gurations or appropriate SW tools for design and C1 = 10uF / 600VDC download of your own confi gurations. Feed- Thru RF capacitor Input Voltage The input voltage range, 4.5 - 14 V, makes the product easy to use in interme- 200mm 800mm diate bus applications when powered by a non-regulated bus converter or a regulated bus converter. See Ordering Information for input voltage range. Conducted EMI test set-up Layout Recommendations The radiated EMI performance of the product will depend on the PWB layout and ground layer design. It is also important to consider the stand-off of the product. If a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. A ground layer will increase the stray capacitance in the PWB and improve the high frequency EMC performance. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 19 of 37 Load OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Input Under Voltage Lockout, UVLO External Capacitors The product monitors the input voltage and will turn-on and turn-off at confi g- Input capacitors: ured levels. The default turn-on input voltage level setting is 4.20 V, whereas The input ripple RMS current in a buck converter is equal to the corresponding turn-off input voltage level is 3.85 V. Hence, the default Eq. 1. I I D 1D , inputRMS load hysteresis between turn-on and turn-off input voltage is 0.35 V. Once an input where I is the output load current and D is the duty cycle. The turn-off condition occurs, the device can respond in a number of ways as load follows: I 2 maximum load ripple current becomes . The ripple current is load divided into three parts, i.e., currents in the input source, external input 1. Continue operating without interruption. The unit will continue to operate capacitor, and internal input capacitor. How the current is divided depends as long as the input voltage can be supported. If the input voltage contin- on the impedance of the input source, ESR and capacitance values in the ues to fall, there will come a point where the unit will cease to operate. capacitors. A minimum capacitance of 300 μF with low ESR is 2. Continue operating for a given delay period, followed by shutdown if the recommended. The ripple current rating of the capacitors must follow fault still exists. The device will remain in shutdown until instructed to Eq. 1. For high-performance/transient applications or wherever the input restart. source performance is degraded, additional low ESR ceramic type capacitors at the input is recommended. The additional input low ESR 3. Initiate an immediate shutdown until the fault has been cleared. The user capacitance above the minimum level insures an optimized performance. can select a specifi c number of retry attempts. The default response from a turn-off is an immediate shutdown of the device. Output capacitors: The device will continuously check for the presence of the fault condition. When powering loads with significant dynamic current requirements, the If the fault condition is no longer present, the product will be re-enabled. voltage regulation at the point of load can be improved by addition of decoupling capacitors at the load. The turn-on and turn-off levels and response can be reconfi gured using the The most effective technique is to locate low ESR ceramic and electrolytic PMBus™ interface. capacitors as close to the load as possible, using several capacitors in Remote Control parallel to lower the effective ESR. The ceramic capacitors will handle high- frequency dynamic load changes while the electrolytic capacitors are used The product is equipped with a remote to handle low frequency dynamic load changes. Ceramic capacitors will control function, i.e., the CTRL pin. The Vext also reduce high frequency noise at the load. remote control can be connected to It is equally important to use low resistance and low inductance PWB either the primary negative input connec- layouts and cabling. CTRL tion (GND) or an external voltage (Vext), External decoupling capacitors are a part of the control loop of the product which is a 3 - 5 V positive supply voltage and may affect the stability margins. in accordance to the SMBus Specifi cation Stable operation is guaranteed for the following total capacitance C in GND O version 2.0. the output decoupling capacitor bank where The CTRL function allows the product Eq. 2. μF. C >@ C ,C >300, 15000@ O min max to be turned on/off by an external device like a semiconductor or mechanical switch. By default the product will turn on when the CTRL pin is left open and The decoupling capacitor bank should consist of capacitors which has a turn off when the CTRL pin is applied to GND. The CTRL pin has an internal capacitance value larger than and has an ESR range of C tC min pull-up resistor. When the CTRL pin is left open, the voltage generated on the Eq. 3. mΩ CTRL pin is max 5.5 V. ESR >ESR , ESR min max@>5, 30@ If the device is to be synchronized to an external clock source, the clock The control loop stability margins are limited by the minimum time constant frequency must be stable prior to asserting the CTRL pin. W of the capacitors. Hence, the time constant of the capacitors should min follow Eq. 4. The product can also be confi gured using the PMBus™ interface to be Eq. 4. “Always on,” or turn on/off can be performed with PMBus™ commands. W tW C ESR 1.5 Ps min min min This relation can be used if your preferred capacitors have parameters Input and Output Impedance outside the above stated ranges in Eq. 2 and Eq.3. The impedance of both the input source and the load will interact with the impedance of the product. It is important that the input source has low char- x If the capacitors capacitance value is one must use at least C C min acteristic impedance. The performance in some applications can be enhanced N capacitors where by addition of external capacitance as described under External Decoupling C C ª º min min Capacitors. If the input voltage source contains signifi cant inductance, the and ESRtESR . N t min « » C C « » addition a capacitor with low ESR at the input of the product will ensure x If the ESR value is ESR ! ESR one must use at least N capacitors stable operation. max of that type where ª º ESR C min N t and Ct . « » ESR N « max» x If the ESR value is ESR  ESR the capacitance value should be min ESR min CtC . min ESR www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 20 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series For a total capacitance outside the above stated range or capacitors that do RSET also sets the maximum not follow the stated above requirements above a re-design of the control output voltage, see section “Output loop parameters will be necessary for robust dynamic operation and stability. VSET Voltage Range Limitation.” The resistor is sensed only during product R SET Control Loop start-up. Changing the resistor value The product uses a voltage-mode synchronous buck controller with a fi xed PREF during normal operation will not frequency PWM scheme. Although the product uses a digital control loop, change the output voltage. The input it operates much like a traditional analog PWM controller. As in the analog voltage must be at least 1 V larger controller case, the control loop compares the output voltage to the desired than the output voltage in order to deliver the correct output voltage. See voltage reference and compensation is added to keep the loop stable and Ordering Information for output voltage range. fast. The resulting error signal is used to drive the PWM logic. Instead of The following table shows recommended resistor values for RSET. Maximum using external resistors and capacitors required with traditional analog 1% tolerance resistors are required. control loops, the product uses a digital Proportional-Integral-Derivative (PID) V [V] R [kΩ] V [V] R [kΩ] O SET O SET compensator in the control loop. The characteristics of the control loop is 0.60 10 1.50 46.4 confi gured by setting PID compensation parameters. These PID settings can 0.65 11 1.60 51.1 be reconfi gured using the PMBus™ interface. 12.1 1.70 56.2 0.70 0.75 13.3 1.80 61.9 Control Loop Compensation Setting 0.80 14.7 1.90 68.1 The products without DLC are by default confi gured with a robust control loop 0.85 16.2 2.00 75 compensation setting (PID setting) which allows for a wide range operation 0.90 17.8 2.10 82.5 of input and output voltages and capacitive loads as defi ned in the section 19.6 2.20 90.9 0.95 External Decoupling Capacitors. For an application with a specifi c input volt- 1.00 21.5 2.30 100 age, output voltage, and capacitive load, the control loop can be optimized for 23.7 2.50 110 1.05 a robust and stable operation and with an improved load transient response. 1.10 26.1 3.00 121 This optimization will minimize the amount of required output decoupling 1.15 28.7 3.30 133 capacitors for a given load transient requirement yielding an optimized cost 1.20 31.6 and minimized board space. The optimization together with load step simula- 1.25 34.8 1.30 tions can be made using the Murata Power Designer software. 38.3 1.40 42.2 Load Transient Response Optimization The output voltage and the maximum output voltage can be pin strapped to The product incorporates a Non-Linear transient Response, NLR, loop that three fi xed values by connecting the VSET pin according to the table below. decreases the response time and the output voltage deviation during a load transient. The NLR results in a higher equivalent loop bandwidth than is pos- V [V] VSET O sible using a traditional linear control loop. The product is pre-confi gured with 0.60 Shorted to PREF appropriate NLR settings for robust and stable operation for a wide range of 1.2 Open “high impedance” input voltage and a capacitive load range as defi ned in the section External 2.5 Logic High, GND as reference Decoupling Capacitors. For an application with a specifi c input voltage, output voltage, and capacitive load, the NLR confi guration can be optimized for a Output Voltage Adjust using PMBus™ robust and stable operation and with an improved load transient response. The output voltage set by pin-strap can be overridden by confi guration fi le or by This will also reduce the amount of output decoupling capacitors and yield using a PMBus™ command. See Electrical Specifi cation for adjustment range. a reduced cost. However, the NLR slightly reduces the effi ciency. In order to When setting the output voltage by confi guration fi le or by a PMBus™ obtain maximal energy effi ciency the load transient requirement has to be met command, the specifi ed output voltage accuracy is valid only when the set by the standard control loop compensation and the decoupling capacitors. The output voltage level falls within the same bin range as the voltage level NLR settings can be reconfi gured using the PMBus™ interface. defi ned by the pin-strap resistor RSET. The applicable bin ranges are defi ned Remote Sense in the table below. Valid accuracy for voltage levels outside the applicable bin The product has remote sense that can be used to compensate for voltage range is two times the specifi ed. drops between the output and the point of load. The sense traces should be Example: located close to the PWB ground layer to reduce noise susceptibility. Due to Nominal VO is set to 1.10 V by RSET = 26.1 kΩ. 1.10 V falls within the bin derating of internal output capacitance the voltage drop should be kept below range 0.988-1.383 V, thus specifi ed accuracy is valid when adjusting VO VDROPMAX = (5.25 – VOUT) / 2. A large voltage drop will impact the electrical within 0.988-1.383V. performance of the regulator. If the remote sense is not needed, +S should be connected to VOUT and −S should be connected to GND. V bin ranges [V] O 0.600 – 0.988 Output Voltage Adjust using Pin-strap Resistor 0.988 – 1.383 Using an external Pin-strap resistor, RSET, the output voltage can be set in the 1.383 – 1.975 range 0.6 V to 3.3 V at 28 different levels shown in the table below. The resistor 1.975 – 2.398 should be applied between the VSET pin and the PREF pin. 2.398 – 2.963 2.963 – 3.753 www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 21 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series interface. A PG delay period is defi ned as the time from when all conditions Output Voltage Range Limitation within the product for asserting PG are met to when the PG signal is actually The output voltage range that is possible to set by confi guration or by the asserted. The default PG delay is set to 10 ms. This value can be reconfi gured PMBus™ interface is limited by the pin-strap resistor RSET. The maximum using the PMBus™ interface. output voltage is set to 110% of the nominal output value defi ned by RSET, V = 1.1 x V . This protects the load from an over voltage due to an O,MAX O,RSET For products with DLC the PG signal is by default asserted directly after accidental wrong PMBus™ command. the DLC operation have been completed. If DLC is disabled the confi gured PG delay will be used. This can be reconfi gured using the PMBus™ interface. Output Voltage Adjust Limitation using PMBus™ In addition to the maximum output voltage limitation by the pin-strap resis- Switching Frequency tor RSET, there is also a limitation in how much the output voltage can be The fundamental switching frequency is 320 kHz, which yields optimal power increased while the output is enabled. If output is disabled then RSET resistor effi ciency. The switching frequency can be set to any value between 200 is the only limitation. kHz and 640 kHz using the PMBus™ interface. The switching frequency will change the effi ciency/power dissipation, load transient response and output Example: ripple. For optimal control loop performance in a product without DLC, the If the output is enabled with output voltage set to 1.0 V, then it is only possible control loop must be re-optimized when changing the switching frequency. to adjust/change the output voltage up to 1.7- V as long as the output is enabled. Synchronization V setting V set range O O Synchronization is a feature that allows multiple products to be synchronized when enabled [V] while enabled [V] to a common frequency. Synchronized products powered from the same 0.000 – 0.988 ~0.2 to >1.2 bus eliminate beat frequencies refl ected back to the input supply, and also 0.988 – 1.383 ~0.2 to >1.7 reduces EMI fi ltering requirements. Eliminating the slow beat frequencies 1.383 – 1.975 ~0.2 to >2.5 (usually <10 kHz) allows the EMI fi lter to be designed to attenuate only the 1.975 – 2.398 ~0.2 to >2.97 synchronization frequency. Synchronization can also be utilized for phase 2.398 – 2.963 ~0.2 to >3.68 spreading, described in section Phase Spreading. 2.963 – 3.753 ~0.2 to >4.65 The products can be synchronized with an external oscillator or one Over Voltage Protection (OVP) product can be confi gured with the SYNC pin as a SYNC Output working as The product includes over voltage limiting circuitry for protection of the load. a master driving the synchronization. All others on the same synchronization The default OVP limit is 15% above the nominal output voltage. If the output bus must be confi gured with SYNC Input. Default confi guration is using the voltage exceeds the OVP limit, the product can respond in different ways: internal clock, independently of signal at the SYNC pin. 1. Initiate an immediate shutdown until the fault has been cleared. The user Phase Spreading can select a specifi c number of retry attempts. When multiple products share a common DC input supply, spreading of the 2. Turn off the high-side MOSFET and turn on the low-side MOSFET. The switching clock phase between the products can be utilized. This dramatically low-side MOSFET remains ON until the device attempts a restart, i.e. the reduces input capacitance requirements and effi ciency losses, since the peak output voltage is pulled to ground level (crowbar function). current drawn from the input supply is effectively spread out over the whole The default response from an overvoltage fault is to immediately shut down switch period. This requires that the products are synchronized. Up to 16 dif- as in 2. The device will continuously check for the presence of the fault ferent phases can be used. condition, and when the fault condition no longer exists the device will be re- The phase spreading of the product can be confi gured using the PMBus™ enabled. For continuous OVP when operating from an external clock for syn- interface. chronization, the only allowed response is an immediate shutdown. The OVP limit and fault response can be reconfi gured using the PMBus™ interface. Parallel Operation (Current Sharing) Paralleling multiple products can be used to increase the output current Under Voltage Protection (UVP) capability of a single power rail. By connecting the GCB pins of each device The product includes output under voltage limiting circuitry for protection of and confi guring the devices as a current sharing rail, the units will share the the load. The default UVP limit is 15% below the nominal output voltage. The current equally, enabling up to 100% utilization of the current capability for UVP limit can be reconfi gured using the PMBus™ interface. each device in the current sharing rail. The product uses a low-bandwidth, fi rst-order digital current sharing by aligning the output voltage of the slave Power Good devices to deliver the same current as the master device. Artifi cial droop The product provides a Power Good (PG) fl ag in the Status Word register that resistance is added to the output voltage path to control the slope of the load indicates the output voltage is within a specifi ed tolerance of its target level and line curve, calibrating out the physical parasitic mismatches due to power no fault condition exists. If specifi ed in section Connections, the product also train components and PWB layout. Up to 7 devices can be confi gured in a provides a PG signal output. The PG pin is active high and by default open-drain given current sharing group. but may also be confi gured as push-pull via the PMBus™ interface. In order to avoid interference with other algorithms executing during By default, the PG signal will be asserted when the output reaches above parallel operation, the dead-time algorithm should be turned off and fi xed 90% of the nominal voltage, and de-asserted when the output falls below dead-times be used. 85% of the nominal voltage. These limits may be changed via the PMBus™ www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 22 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series via the PMBus™ interface, which will overwrite any values loaded during the Phase Adding and Shedding for Parallel Operation initialization procedure. During periods of light loading, it may be benefi cial to disable one or more phases (modules) in order to eliminate the current drain and switching losses Soft-start Power Up associated with those phases, resulting in higher effi ciency. The product offers The soft-start control introduces a time-delay before allowing the output the ability to add and drop phases (modules) using a PMBus™ command voltage to rise. Once the initialization time has passed the device will wait for in response to an observed load current change. All phases (modules) in a the confi gured delay period prior to starting to ramp its output. After the delay current share rail are considered active prior to the current sharing rail ramp period has expired, the output will begin to ramp towards its target voltage to power-good. Phases can be dropped after power-good is reached. Any according to the confi gured soft-start ramp time. member of the current sharing rail can be dropped. If the reference module is dropped, the remaining active module with the lowest member position will The default settings for the soft-start delay period and the soft-start ramp become the new reference. Additionally, any change to the number of mem- time is 10 ms. Hence, power-up is completed within 20 ms in default con- bers of a current sharing rail will precipitate autonomous phase distribution fi guration using remote control. When the soft-start delay time is set to 0 ms, within the rail where all active phases realign their phase position based on the module will begin its ramp-up after the internal circuitry has initialized their order within the number of active members. If the members of a current (approximately 2 ms). It is generally recommended to set the soft-start ramp-up sharing rail are forced to shut down due to an observed fault, all members of time to a value greater than 500 μs to prevent inadvertent fault conditions due the rail will attempt to re-start simultaneously after the fault has cleared. to excessive inrush current. The acctual minimum ramp-up time will however normally be limited by the control loop settings and ramp-up times of internal Effi ciency Optimized Dead Time Control interface voltages in the controller circuit to approximately 2 ms. The soft-start The product utilizes a closed loop algorithm to optimize the dead-time applied power up of the product can be reconfi gured using the PMBus™ interface. between the gate drive signals for the switch and synch FETs. The algorithm constantly adjusts the deadtime non-overlap to minimize the duty cycle, thus maximizing effi ciency. This algorithm will null out deadtime differences due to component variation, temperature and loading effects. The algorithm can be VIN confi gured via the PMBus™ interface. CTRL Over Current Protection (OCP) The product includes current limiting circuitry for protection at continuous overload. The following OCP response options are available: VOUT Initialization Delay Ramp 1. Initiate a shutdown and attempt to restart an infi nite number of times with time time time a preset delay period between attempts. Illustration of Power Up Procedure 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. Output Voltage Sequencing 3. Continue operating for a given delay period, followed by shutdown if the A group of products may be confi gured to power up in a predetermined fault still exists. sequence. This feature is especially useful when powering advanced proces- sors, FPGAs, and ASICs that require one supply to reach its operating voltage 4. Continue operating through the fault (this could result in permanent prior to another. Multi-product sequencing can be achieved by confi guring the damage to the power supply). start delay and rise time of each device through the PMBus™ interface and by 5. Initiate an immediate shutdown. using the CTRL start signal. The default response from an over current fault is an immediate shutdown VOUT of the device. The device will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be V1 re-enabled. The load distribution should be designed for the maximum output short circuit current specifi ed. The OCP limit and response of the product can be reconfi gured using the PMBus™ interface. V2 Initialization Procedure The product follows a specifi c internal initialization procedure after power is applied to the VIN pin: 1. Status of the address and output voltage pin-strap pins are checked and t values associated with the pin settings are loaded to RAM. Illustration of Output Voltage Sequencing. 2. Values stored in the Murata default non-volatile memory are loaded to Voltage Tracking RAM. This overwrites any previously loaded values. The product integrates a lossless tracking scheme that allows its output to 3. Values stored in the user non-volatile memory are loaded to RAM. This track a voltage that is applied to the VTRK pin with no external components overwrites any previously loaded values. required. During ramp-up, the output voltage follows the VTRK voltage until Once the initialization process is completed, the product is ready to be the preset output voltage level is met. The product offers two modes of track- enabled using the CTRL pin. The product is also ready to accept commands ing as follows: www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 23 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series 1. Coincident. This mode confi gures the product to ramp its output voltage at Group Communication Bus the same rate as the voltage applied to the VTRK pin. The Group Communication Bus, GCB, is used to communicate between products. This dedicated bus provides the communication channel between VOUT devices for features such as sequencing, fault spreading, and current sharing. The GCB solves the PMBus™ data rate limitation. The GCB pin on all devices MASTER in an application should be connected together. A pull-up resistor is required on the common GCB in order to guarantee the rise time as follows: Eq. 5.  = R C ≤ 1μs, SLAVE GCB GCB where R is the pull up resistor value and C is the bus loading. The GCB GCB pull-up resistor should be tied to an external supply voltage in range from 3.3 to 5 V, which should be present priorμ to or during power-up. t Illustration of Coincident Voltage Tracking. If exploring untested compensation or deadtime confi gurations, it is recom- mended that 27 Ω series resistors are placed between the GCB pin of each 2. Ratiometric. This mode confi gures the product to ramp its output voltage product and the common GCB connection. This will avoid propagation of faults at a rate that is a percentage of the voltage applied to the VTRK pin. The between products potentially caused by hazardous confi guration settings. default setting is 50%, but a different tracking ratio may be set by an When the confi gurations of the products are settled the series resistors can external resistive voltage divider or through the PMBus™ interface. be removed. VOUT The GCB is an internal bus, such that it is only connected across the mod- ules and not the PMBus™ system host. GCB addresses are assigned on a rail MASTER level, i.e. modules within the same current sharing group share the same GCB address. Addressing rails across the GCB is done with a 5 bit GCB ID, yielding a theoretical total of 32 rails that can be shared with a single GCB bus. SLAVE Fault Spreading The product can be confi gured to broadcast a fault event over the GCB bus to the other devices in the group. When a non-destructive fault occurs and the t device is confi gured to shut down on a fault, the device will shut down and broadcast the fault event over the GCB bus. The other devices on the GCB bus Illustration of Ratiometric Voltage Tracking will shut down together if confi gured to do so, and will attempt to re-start in The master device in a tracking group is defi ned as the device that has the their prescribed order if confi gured to do so. highest target output voltage within the group. This master device will control Over Temperature Protection (OTP) the ramp rate of all tracking devices and is not confi gured for tracking mode. The products are protected from thermal overload by an internal over tempera- All of the CTRL pins in the tracking group must be connected and driven by ture shutdown function in the controller circuit N1, located at position P2 (see a single logic source. It should be noted that current sharing groups that are section Thermal Consideration). Some of the products that this specifi cation also confi gured to track another voltage do not offer pre-bias protection; a covers use the temperature at position P2 (TP2) as a reference for specifi ed minimum load should therefore be enforced to avoid the output voltage from OTP threshold and some use position P1 (TP1) as a reference for specifi ed OTP being held up by an outside force. threshold. See the Over Temperature Protection section in the electrical specifi - Voltage Margining Up/Down cation for each product. The product can adjust its output higher or lower than its nominal voltage Products with P1 as reference for OTP: setting in order to determine whether the load device is capable of operating When TP1 as defi ned in thermal consideration section exceeds approxi- over its specifi ed supply voltage range. This provides a convenient method for mately 120 °C the product will shut down. The specifi ed OTP threshold and dynamically testing the operation of the load circuit over its supply margin or hysteresis are valid for worst case operation regarding cooling conditions, range. It can also be used to verify the function of supply voltage supervisors. input voltage and output voltage. The actually confi gured default value in the Margin limits of the nominal output voltage ±5% are default, but the margin controller circuit in position P2 is 110 °C, but at worst case operation the limits can be reconfi gured using the PMBus™ interface. temperature is approximately 10 °C higher at position P1. At light load the temperature is approximately the same in position P1 and P2. This means the Pre-Bias Startup Capability OTP threshold and hysteresis will be lower at light load conditions when P1 is Pre-bias startup often occurs in complex digital systems when current from used as a reference for OTP. another power source is fed back through a dual-supply logic component, such as FPGAs or ASICs. The product family incorporates synchronous recti- Products with P2 as reference OTP: fi ers, but will not sink current during startup, or turn off, or whenever a fault When TP2 as defi ned in thermal consideration section exceeds 120°C the shuts down the product in a pre-bias condition. Pre-bias protection is not product will shut down. For products with P2 as a reference for OTP the con- offered for current sharing groups that also have voltage tracking enabled. fi gured default value in the controller circuit in position P2 is 120°C. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 24 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series The OTP threshold, hysteresis, and fault response of the product can be 3. Continue operating for a given delay period, followed by shutdown if the reconfi gured using the PMBus™ interface. The fault response can be confi g- fault still exists. ured as follows: 4. Continue operating through the fault (this could result in permanent 1. Initiate a shutdown and attempt to restart an infi nite number of times with damage to the power supply). a preset delay period between attempts (default confi guration). 5. Initiate an immediate shutdown. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. Thermal Consideration General AIR FLOW The product is designed to operate in different thermal environments and suf- fi cient cooling must be provided to ensure reliable operation. Top view Bottom view Cooling is achieved mainly by conduction, from the pins to the host board, and convection, which is dependent on the airfl ow across the product. P2 Increased airfl ow enhances the cooling of the product. P1 The Output Current Derating graph found in the Output section for each model provides the available output current vs. ambient air temperature and air velocity at specifi ed VI. Temperature positions and air fl ow direction. The product is tested on a 254 x 254 mm, 35 μm (1 oz), test board mounted vertically in a wind tunnel with a cross-section of 608 x 203 mm. The test board has 8 layers. AIR FLOW Proper cooling of the product can be verifi ed by measuring the temperature at positions P1 and P2. The temperature at these positions should not exceed P1 the max values provided in the table below. P2 Note that the max value is the absolute maximum rating (non destruction) and that the electrical Output data is guaranteed up to TP1 +95°C. DeŢ nition of product operating temperature SIP Version:Temperature positions and air fl ow direction. The product operating temperatures are used to monitor the temperature DeŢ nition of reference temperature TP1 of the product, and proper thermal conditions can be verifi ed by measuring the temperature at positions P1 and P2. The temperature at these positions The reference temperature is used to monitor the temperature limits of the (TP1, TP2) should not exceed the maximum temperatures in the table below. product. Temperature above maximum TP1, measured at the reference point The number of measurement points may vary with different thermal design P1 is not allowed and may cause degradation or permanent damage to the product. TP1 is also used to defi ne the temperature range for normal operat- and topology. Temperatures above maximum TP1, measured at the reference ing conditions. TP1 is defi ned by the design and used to guarantee safety point P1 are not allowed and may cause permanent damage. It should also be noted that depending on setting of the over temperature protection (OTP) margins, proper operation and high reliability of the product. and operating conditions, the product may shut down before the maximum allowed temperature at TP1 is reached. Position Description Max Temp. * P1 Reference point, L1, inductor 125°C * P2 N1, control circuit 125°C * A guard band of 5 °C is applied to the maximum recorded component temperatures when calculating output current derating curves. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 25 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Pin layout, top view (component placement for illustration only). SIP Version: Pin layout, top view (component placement for illustration only). Pin Designation Function Pin Designation Function 1A VIN Input Voltage 1A VIN Input Voltage 2A GND Power Ground 2A GND Power Ground 3A VOUT Output Voltage 3A VOUT Output Voltage Voltage Tracking input or Power 4A +S Positive sense 4A VTRK or PG* Good 4B −S Negative sense 4B PREF Pin-strap reference 5A VSET Output voltage pin-strap 5A +S Positive sense 5B VTRK Voltage Tracking input 5B −S Negative sense 6A SALERT PMBus Alert 6A SA0 PMBus address pin-strap 6B SDA PMBus Data 6B GCB Group Communication Bus 7A SCL PMBus Clock 7A SCL PMBus Clock 7B SA1 PMBus address pin-strap 1 7B SDA PMBus Data 8A SA0 PMBus address pin-strap 0 8A VSET Output voltage pin-strap 8B SYNC Synchronization I/O 8B SYNC Synchronization I/O 9A PG Power Good 9A SALERT PMBus Alert 9B CTRL Remote Control 9B CTRL Remote Control 10A GCB Group Communication Bus 10B PREF Pin-strap reference OKDH-T/20-W12-001-C, OKDY-T/20-W12-001-C, OKDH-T/25-W12-001-C, OKDY-T/25-W12-001-C: Pin 4A = VTRK pin. OKDH-T/20-W12G-001-C, OKDY-T/20-W12G-001-C, OKDH-T/25-W12G-001-C, OKDY-T/25-W12G-001-C: Pin 4A = PG pin. For these products the PG pin is internally tied to the VTRK input of the products’ controller. Typically the VTRK input bias current will be equivalent to a 50 kΩ pull-down resistor. This should be considered when choosing pull-up resistor for the PG signal. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 26 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Avoid current carrying planes under the pin-strap resistors and the Unused input pins PMBus™ signals. Unused SDA, SCL and GCB pins should still have pull-up resistors as specifi ed. The capacitor CI (or capacitors implementing it) should be placed as close to the input pins as possible. Unused VTRK or SYNC pins should be left open or connected to the PREF pin. Capacitor CO (or capacitors implementing it) should be placed close to the Unused CTRL pin can be left open due to internal pull-up. load. VSET and SA0/SA1 pins must be used. These pins must have pin-strap Care should be taken in the routing of the connections from the sensed resistors or strapping settings as specifi ed. output voltage to the S+ and S– terminals. These sensing connections should PWB layout considerations be routed as a differential pair, preferably between ground planes which are The pin-strap resistors, RSET, and RSA0/RSA1 should be placed as close to not carrying high currents. The routing should avoid areas of high electric or the product as possible to minimize loops that may pick up noise. magnetic fi elds. Typical Application Circuit Standalone operation with PMBus™ communication. Top view of product footprint. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 27 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Typical Application Circuit (SIP version) Standalone operation with PMBus™ communication. Top view of product footprint. Typical Application Circuit (Parallel Operation) Parallel operation. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 28 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series fault has occurred. Automatic store to Flash memory following a fault is trig- PMBus™ interface gered when any fault threshold level is exceeded, provided that the specifi c This product provides a PMBus™ digital interface that enables the user to fault response is to shut down. Writing to Flash memory is not allowed if the confi gure many aspects of the device operation as well as to monitor the device is confi gured to restart following the specifi c fault condition. It should input and output voltages, output current and device temperature. The product 2 also be noted that the device supply voltage must be maintained during the can be used with any standard two-wire I C or SMBus host device. In addition, time the device is writing data to Flash memory; a process that requires the product is compatible with PMBus™ version 1.1 and includes an SALERT between 700-1400 μs depending on whether the data is set up for a block line to help mitigate bandwidth limitations related to continuous fault monitor- write. Undesirable results may be observed if the input voltage of the product ing. The product supports 100 kHz bus clock frequency only. The PMBus™ drops below 3.0 V during this process. signals, SCL, SDA and SALERT require passive pull-up resistors as stated in the SMBus Specifi cation. Pull-up resistors are required to guarantee the rise Non-Volatile Memory (NVM) time as follows: The product incorporates two Non-Volatile Memory areas for storage of the sup- Eq. 6.  = R C ≤ 1μs, p p ported PMBus™ commands; the Default NVM and the User NVM. where R is the pull-up resistor value and C is the bus loading, the p p The Default NVM is pre-loaded with Murata factory default values. The maximum allowed bus load is 400 pF. The pull-up resistor should be tied to Default NVM is write-protected and can be used to restore the Murata factory an external supply voltage in range from 2.7 to 5.5 V, which should be present default values through the command RESTORE_DEFAULT_ALL. prior to or during power-up. If the proper power supply is not available, The User NVM is pre-loaded with Murata factory default values. The User voltage dividers may be applied. Note that in this case, the resistance in the NVM is writable and open for customization. The values in NVM are loaded equation above corresponds to parallel connection of the resistors forming the into operational RAM during initialization according to section “Initialization voltage divider. Procedure”, where after commands can be changed through the PMBus™ Interface. The STORE_USER_ALL command will store the changed param- Monitoring via PMBus™ eters to the User NVM. It is possible to monitor a wide variety of parameters through the PMBus™ INITIALIZATION interface. Fault conditions can be monitored using the SALERT pin, which will User NVM be asserted when any number of pre-confi gured fault or warning conditions Factory default STORE_USER_ALL occurs. It is also possible to continuously monitor one or more of the power Customizable conversion parameters including but not limited to the following: RESTORE USER ALL Input voltage (READ_VIN) Output voltage (READ_VOUT) INITIALIZATION Default NVM Output current (READ_IOUT) RAM Factory default RESTORE_DEFAULT_ALL Internal junction temperature (READ_TEMPERATURE_1) Write-protected Switching frequency (READ_FREQUENCY) WRITE Duty cycle (READ_DUTY_CYCLE) PMBus interface READ In the default confi guration monitoring is enabled also when the output voltage is disabled. This can be changed in order to reduce standby power consumption. Software tools for design and production Snap shot parameter capture Murata provides software tools for confi guration and monitoring of this prod- This product offers a special feature that enables the user to capture uct via the PMBus™ interface. For more information please contact your local parametric data during normal operation or following a fault. The following Murata sales representative. parameters are stored: PMBus™ addressing Input voltage The PMBus™ address should be confi gured with resistors connected Output voltage between the SA0/SA1 pins and the PREF pin, as shown in the fi gure below. Recommended resistor values for hard-wiring PMBus™ addresses are shown Output current in the table. 1% tolerance resistors are required. Internal junction temperature Switching frequency SA0 Duty cycle SA1 Status registers R R SA1 SA0 The Snapshot feature enables the user to read the parameters via the PREF PMBus™ interface during normal operation, although it should be noted that reading the 22 bytes will occupy the bus for some time. The Snapshot enables the user to store the snapshot parameters to Flash memory in response to a pending fault as well as to read the stored data from Flash memory after a Schematic of connection of address resistor. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 29 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Index R [kΩ] Index R [kΩ] SA SA Address (decimal) Comment 0 10 13 34.8 72-75 Unrestricted addresses 1 11 14 38.3 97 SMBus Device Default Address 2 12.1 15 42.2 120-123 10-bit slave addressing 3 13.3 16 46.4 124-127 Reserved for future use 4 14.7 17 51.1 2 I C/SMBus – Timing 5 16.2 18 56.2 6 17.8 19 61.9 7 19.6 20 68.1 8 21.5 21 75 9 23.7 22 82.5 10 26.1 23 90.9 11 28.7 24 100 12 31.6 The PMBus™ address follows the equation below: Eq. 7. PMBus™ Address (decimal) = 25 x (SA1 index) + (SA0 index) The user can theoretically confi gure up to 625 unique PMBus™ addresses, however the PMBus™ address range is inherently limited to 128. Therefore, Setup and hold times timing diagram the user should use index values 0 - 4 on the SA1 pin and the full range of The setup time, tset, is the time data, SDA, must be stable before the rising index values on the SA0 pin, which will provide 125 device address combina- edge of the clock signal, SCL. The hold time thold, is the time data, SDA, must tions. The user shall also be aware of further limitations of the address space be stable after the rising edge of the clock signal, SCL. If these times are vio- as stated in the SMBus Specifi cation. Note that address 0x4B is allocated for lated incorrect data may be captured or meta-stability may occur and the bus production needs and cannot be used. communication may fail. When confi guring the product, all standard SMBus Products with no SA1 pin have an internally defi ned SA1 index as follows. protocols must be followed, including clock stretching. Refer to the SMBus specifi cation, for SMBus electrical and timing requirements. Product SA1 index OKDX-T/20-W12 (non SIP) 3 This product does not support the BUSY fl ag in the status commands to indicate product being too busy for SMBus response. Instead a bus-free time Optional PMBus™ Addressing delay according to this specifi cation must occur between every SMBus trans- Alternatively the PMBus™ address can be defi ned by connecting the SA0/SA1 mission (between every stop & start condition). In case of storing the RAM pins according to the table below. SA1 = open for products with no SA1 pin. content into the internal non-volatile memory (commands STORE_USER_ALL SA0 and STORE_DEFAULT_ALL) an additional delay of 100 ms has to be inserted. low open high A 100 ms delay should be inserted after a restore from internal non-volatile low 20h 21h 22h memory (commands RESTORE_DEFAULT_ALL and RESTORE_USER_ALL). open 23h 24h 25h SA1 PMBus™ Commands high 26h 27h Reserved The products are PMBus™ compliant. The following table lists the imple- Low = Shorted to PREF mented PMBus™ read commands. For more detailed information see Open = High impedance PMBus™ Power System Management Protocol Specifi cation; Part I – General High = Logic high, GND as reference, Requirements, Transport and Electrical Interface and PMBus™ Power System Logic High deŢ nitions see Electrical SpeciŢ cation Management Protocol; Part II – Command Language. Reserved Addresses Designation Cmd Impl Address 4Bh is allocated for production needs and cannot be used. Standard PMBus™ Commands Control Commands Addresses listed in the table below are reserved or assigned according to PAGE 00h No the SMBus specifi cation and may not be usable. Refer to the SMBus specifi - OPERATION 01h Yes cation for further information. ON_OFF_CONFIG 02h Yes Address (decimal) Comment WRITE_PROTECT 10h No Output Commands 0 General Call Address / START byte VOUT_MODE (Read Only) 20h Yes 1 CBUS address VOUT_COMMAND 21h Yes 2 Address reserved for different bus format VOUT_TRIM 22h Yes 3-7 Reserved for future use VOUT_CAL_OFFSET 23h Yes 8 SMBus Host VOUT_MAX 24h Yes 9-11 Assigned for Smart Battery VOUT_MARGIN_HIGH 25h Yes 12 SMBus Alert Response Address VOUT_MARGIN_LOW 26h Yes 40 Reserved for ACCESS.bus host VOUT_TRANSITION_RATE 27h Yes 44-45 Reserved by previous versions of the SMBus specifi cation VOUT_DROOP 28h Yes 55 Reserved for ACCESS.bus default address MAX_DUTY 32h Yes 64-68 Reserved by previous versions of the SMBus specifi cation www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 30 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Designation Cmd Impl Designation Cmd Impl FREQUENCY_SWITCH 33h Yes Identifi cation Commands VIN_ON 35h No PMBUS_REVISION 98h Yes VIN_OFF 36h No MFR_ID 99h Yes IOUT_CAL_GAIN 38h Yes MFR_MODEL 9Ah Yes IOUT_CAL_OFFSET 39h Yes MFR_REVISION 9Bh Yes VOUT_SCALE_LOOP 29h No MFR_LOCATION 9Ch Yes VOUT_SCALE_MONITOR 2Ah No MFR_DATE 9Dh Yes COEFFICIENTS 30h No MFR_SERIAL 9Eh Yes Fault Limit Commands Supervisory Commands POWER_GOOD_ON 5Eh Yes STORE_DEFAULT_ALL 11h Yes POWER_GOOD_OFF 5Fh No RESTORE_DEFAULT_ALL 12h Yes VOUT_OV_FAULT_LIMIT 40h Yes STORE_USER_ALL 15h Yes VOUT_OV_WARN_LIMIT 42h No RESTORE_USER_ALL 16h Yes VOUT_UV_WARN_LIMIT 43h No Product Specifi c Commands VOUT_UV_FAULT_LIMIT 44h Yes Output Commands IOUT_OC_FAULT_LIMIT 46h Yes XTEMP_SCALE D9h No IOUT_OC_WARN_LIMIT 4Ah No XTEMP_OFFSET DAh No IOUT_UC_FAULT_LIMIT 4Bh Yes Time Setting Commands OT_FAULT_LIMIT 4Fh Yes POWER_GOOD_DELAY D4h Yes OT_WARN_LIMIT 51h Yes Fault limit Commands UT_WARN_LIMIT 52h Yes IOUT_AVG_OC_FAULT_LIMIT E7h Yes UT_FAULT_LIMIT 53h Yes IOUT_AVG_UC_FAULT_LIMIT E8h Yes VIN_OV_FAULT_LIMIT 55h Yes Fault Response Commands VIN_OV_WARN_LIMIT 57h Yes MFR_IOUT_OC_FAULT_RESPONSE E5h Yes VIN_UV_WARN_LIMIT 58h Yes MFR_IOUT_UC_FAULT_RESPONSE E6h Yes VIN_UV_FAULT_LIMIT 59h Yes OVUV_CONFIG D8h Yes Fault Response Commands Confi guration and Control Commands VOUT_OV_FAULT_RESPONSE 41h Yes MFR_CONFIG D0h Yes VOUT_UV_FAULT_RESPONSE 45h Yes USER_CONFIG D1h Yes OT_FAULT_RESPONSE 50h Yes MISC_CONFIG E9h Yes UT_FAULT_RESPONSE 54h Yes TRACK_CONFIG E1h Yes VIN_OV_FAULT_RESPONSE 56h Yes PID_TAPS D5h Yes * VIN_UV_FAULT_RESPONSE 5Ah Yes PID_TAPS_CALC F2h Yes IOUT_OC_FAULT_RESPONSE 47h No INDUCTOR D6h Yes IOUT_UC_FAULT_RESPONSE 4Ch No NLR_CONFIG D7h Yes Time setting Commands TEMPCO_CONFIG DCh Yes TON_DELAY 60h Yes IOUT_OMEGA_OFFSET BEh Yes TON_RISE 61h Yes DEADTIME DDh Yes TOFF_DELAY 64h Yes DEADTIME_CONFIG DEh Yes TOFF_FALL 65h Yes DEADTIME_MAX BFh Yes TON_MAX_FAULT_LIMIT 62h No SNAPSHOT EAh Yes Status Commands (Read Only) SNAPSHOT_CONTROL F3h Yes CLEAR_FAULTS 03h Yes DEVICE_ID E4h Yes STATUS_BYTE 78h Yes USER_DATA_00 B0h Yes STATUS_WORD 79h Yes Group Commands STATUS_VOUT 7Ah Yes SEQUENCE E0h Yes STATUS_IOUT 7Bh Yes GCB_CONFIG D3h Yes STATUS_INPUT 7Ch Yes GCB_GROUP E2h Yes STATUS_TEMPERATURE 7Dh Yes ISHARE_CONFIG D2h Yes STATUS_CML 7Eh Yes PHASE_CONTROL F0h Yes STATUS_MFR_SPECIFIC 80h Yes Supervisory Commands Monitor Commands (Read Only PRIVATE_PASSWORD FBh Yes READ_VIN 88h Yes PUBLIC_PASSWORD FCh Yes READ_VOUT 8Bh Yes UNPROTECT FDh Yes READ_IOUT 8Ch Yes SECURITY_LEVEL FAh Yes READ_TEMPERATURE_1 8Dh Yes Notes: READ_TEMPERATURE_2 8Eh No Cmd is short for Command. READ_FAN_SPEED_1 90h No Impl is short for Implemented. READ_DUTY_CYCLE 94h Yes * These commands are available in products without DLC. READ_FREQUENCY 95h Yes ** These commands are available in products with DLC. Group Commands INTERLEAVE 37h Yes PHASE_CONTROL F0h Yes www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 31 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-THROUGH-HOLE MOUNT All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 32 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-SURFACE MOUNT All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 33 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-SIP VERSION All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 34 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Soldering Information - Surface Mounting and Hole Mount Maximum Product Temperature Requirements Top of the product PWB near pin 10B is chosen as reference location for the through Pin in Paste Assembly maximum (peak) allowed product temperature (TPRODUCT) since this will likely The product is intended for forced convection or vapor phase refl ow soldering be the warmest part of the product during the refl ow process. in SnPb or Pb-free processes. The refl ow profi le should be optimised to avoid excessive heating of the SnPb solder processes product. It is recommended to have a suffi ciently extended preheat time to For SnPb solder processes, the product is qualifi ed for MSL 1 according to ensure an even temperature across the host PWB and it is also recommended IPC/JEDEC standard J STD 020C. to minimize the time in refl ow. During refl ow TPRODUCT must not exceed 225 °C at any time. A no-clean fl ux is recommended to avoid entrapment of cleaning fl uids in cavities inside the product or between the product and the host board, since Pb-free solder processes cleaning residues may affect long time reliability and isolation voltage. For Pb-free solder processes, the product is qualifi ed for MSL 3 according to General reflow process specifications SnPb eutectic Pb-free IPC/JEDEC standard J-STD-020C. Average ramp-up (T ) 3°C/s max 3°C/s max PRODUCT During refl ow TPRODUCT must not exceed 260 °C at any time. Typical solder melting (liquidus) T 183°C 221°C L temperature Dry Pack Information Minimum refl ow time above T 60 s 60 s L Minimum pin temperature T 210°C 235°C Products intended for Pb-free refl ow soldering processes are delivered in PIN Peak product temperature T 225°C 260°C PRODUCT standard moisture barrier bags according to IPC/JEDEC standard J STD 033 Average ramp-down (T ) 6°C/s max 6°C/s max PRODUCT (Handling, packing, shipping and use of moisture/refl ow sensitivity surface Maximum time 25°C to peak 6 minutes 8 minutes mount devices). Minimum Pin Temperature Recommendations Using products in high temperature Pb-free soldering processes requires Pin number 2B is chosen as reference location for the minimum pin tempera- dry pack storage and handling. In case the products have been stored in an uncontrolled environment and no longer can be considered dry, the modules must be baked according to J STD 033. Temperature T maximum PRODUCT Thermocoupler Attachment T minimum Pin PIN profile T L Pin 2A for measurement of minimum Pin (solder joint) Product temperature T PIN profile Time in reflow Time in preheat / soak zone Time 25°C to peak Time ture recommendation since this will likely be the coolest solder joint during the refl ow process. SnPb solder processes For SnPb solder processes, a pin temperature (TPIN) in excess of the solder  melting temperature, (TL, 183°C for Sn63Pb37) for more than 60 seconds Pin 4B for measurement of maximum and a peak temperature of 220°C is recommended to ensure a reliable solder Product temperature T PRODUCT joint. For dry packed products only: depending on the type of solder paste Soldering Information - Hole Mounting and fl ux system used on the host board, up to a recommended maximum The hole mounted product is intended for plated through hole mounting by temperature of 245°C could be used, if the products are kept in a controlled wave or manual soldering. The pin temperature is specifi ed to maximum to environment (dry pack handling and storage) prior to assembly. 270°C for maximum 10 seconds. Lead-free (Pb-free) solder processes A maximum preheat rate of 4°C/s and maximum preheat temperature of For Pb-free solder processes, a pin temperature (TPIN) in excess of the solder 150°C is suggested. When soldering by hand, care should be taken to avoid melting temperature (TL, 217 to 221°C for SnAgCu solder alloys) for more direct contact between the hot soldering iron tip and the pins for more than a than 60 seconds and a peak temperature of 245°C on all solder joints is few seconds in order to prevent overheating. recommended to ensure a reliable solder joint. A no-clean fl ux is recommended to avoid entrapment of cleaning fl uids in cavities inside the product or between the product and the host board. The cleaning residues may affect long time reliability and isolation voltage. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 35 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Delivery Package Information The products are delivered in antistatic carrier tape (EIA 481 standard). Carrier Tape Specifications Material Antistatic PS Surface resistance <107 Ohm/square Bakeability The tape is not bakable Tape width, W 44 mm [1.73 inch] Pocket pitch, P 24 mm [0.95 inch] 1 Pocket depth, K 12.4 mm [0.488 inch] 0 Reel diameter 381 mm [15 inch] Reel capacity 200 products /reel Reel weight 1.7 kg/full reel www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 36 of 37 OKDx-T/20-W12-xxx-C 20A Digital PoL DC-DC Converter Series Soldering Information - Hole Mounting (SIP version) The product is intended for plated through hole mounting by wave or manual soldering. The pin temperature is specifi ed to maximum to 270°C for maxi- mum 10 seconds. A maximum preheat rate of 4°C/s and maximum preheat temperature of 150°C is suggested. When soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. A no-clean fl ux is recommended to avoid entrapment of cleaning fl uids in cavities inside the product or between the product and the host board. The cleaning residues may affect long time reliability and isolation voltage. Delivery Package Information (SIP version) The products are delivered in antistatic trays. Tray Specifications Material Antistatic Polyethylene foam 5 11 Surface resistance 10 < Ohms/square <10 Bakability The trays are not bakeable Tray thickness 15 mm [0.709 inch] Box capacity 100 products, 2 full trays/box) Tray weight 35 g empty tray, 549 g full tray This product is subject to the following operating requirements Murata Power Solutions, Inc. and the Life and Safety Critical Application Sales Policy: 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 U.S.A. Refer to: http://www.murata-ps.com/requirements/ ISO 9001 and 14001 REGISTERED Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. © 2016 Murata Power Solutions, Inc. www.murata-ps.com/support MDC_OKDx-T/20-W12-xxx-C.A05 Page 37 of 37