MURATA POWER SOLUTIONS OKDX-T/50-W12-001-C

OKDx-T/50-W12-C www.murata-ps.com 50A Digital PoL DC-DC Converter Series T Typical units ypical units FEATURES  Small package: SMD/TH: 30.85 x 20.0 x 8.2 mm PRODUCT OVERVIEW (1.215 x 0.787 x 0.323 in); SIP: 33.0 x 7.6 x 18.1 mm (1.30 x 0.30 x 0.713 in) The OKDx-T/50-W12 series are high effi - ments. Apart from standard PoL performance  0.6 V - 3.3 V output voltage range ciency, digital point-of-Load (PoL) DC-DC and safety features like OVP, OCP, OTP, and power converters capable of delivering UVLO, these digital converters have advanced  High effi ciency, typ. 97.2% at 5Vin, 3.3Vout half 50A/165W. Available in three different pack- features: digital current sharing (full power, load age formats, through-hole, single-in-line, no derating), non-linear transient response,  Confi guration and monitoring via PMBus™ and surface mount, these converters have a optimized dead time control, synchronization,  Adaptive compensation of PWM control loop & typical effi ciency of 97.2%. PMBus™ compat- and phase spreading. These converters are fast loop transient response ibility allows monitoring and confi guration of ideal for use in telecommunications, network-  Synchonization & phase spreading critical system-level performance require- ing, and distributed power applications.  Current sharing, voltage tracking & voltage margining Power Management via PMBus™ Applications  Voltage setting via pin-strap or PMBus™   Confi gurable soft-start/stop Distributed power architectures  MTBF 14.2 Mh   Confi gurable output voltage (Vout) and voltage Intermediate bus voltage applications  Non-Linear Response for reduction of decou- margins (Margin low and Margin high)  Servers and storage applications pling capacitor  Confi gurable protection limits for OVP, input over  Network equipment  Remote control & power good voltage, input under voltage, over current, on/off,  and temperature Output short-circuit, output over voltage, & over temperature protection  Status monitor Vout, Iout, Vin, Temp, Power  Certifi ed to UL/IEC 60950-1 good, and On/Off PART NUMBER STRUCTURE OKD x - T / 50 - W12 E - xxx - C Digital Non-isolated PoL RoHS Hazardous Substance Compliance C = RoHS-6 (does not claim EU RoHS exemption Y = Surface Mount 7b – lead in solder) H = Horizontal Mount Through-Hole X = SIP Software Confi guration Digits (001 is positive turn-on logic) Trimmable Output (002 is negative turn-on logic)* Voltage Range 0.6 - 3.3Vdc E = Long pin length (5.5mm) Blank = Standard length (4.0mm) *Special quantity order is required; Maximum Rated Output contact Murata Power Solutions for Input Voltage Range Current in Amps MOQ and lead times. 4.5-14Vdc PM www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 1 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series ORDERING GUIDE Model Number Output OKDY-T/50-W12-001-C OKDH-T/50-W12-001-C OKDX-T/50-W12-001-C 0.6-3.3 V, 50 A/ 165 W OKDX-T/50-W12E-001-C OKDH-T/50-W12-002-C OKDX-T/50-W12-002-C Absolute Maximum Ratings Characteristics Min Typ Max Unit TP2 Operating temperature (see Thermal Consideration section) -40 125 °C TS Storage temperature -40 125 °C VI Input voltage (See Operating Information Section for input and output voltage relations) -0.3 16 V Logic I/O voltage CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, GCB, PG -0.3 6.5 V Ground voltage differential -S, PREF, GND -0.3 0.3 V Analog pin voltage VO, +S, VTRK -0.3 6.5 V General and Safety Conditions Min Typ Max Unit Safety Designed for UL/IEC/EN 60950 1 Calculated MTBF Telcordia SR-332, Issue 2 Method 1 14.2 Mhrs Stress in excess of Absolute Maximum Ratings may cause permanent default confi guration fi le, unless otherwise specifi ed. The default damage. Absolute Maximum Ratings, sometimes referred to as no confi guration fi le is designed to fi t most application needs with focus destruction limits, are normally tested with one parameter at a time on high effi ciency. If different characteristics are required it is pos- exceeding the limits in the Electrical Specifi cation. If exposed to stress sible to change the confi guration fi le to optimize certain performance above these limits, function and performance may degrade in an characteristics. Note that current sharing operation requires changed unspecifi ed manner. confi guration fi le. In this Technical specifi cation examples are included to show the Confi guration File possibilities with digital control. See Operating Information section for This product is designed with a digital control circuit. The control information about trade offs when optimizing certain key performance circuit uses a confi guration fi le which determines the functionality characteristics. and performance of the product. The Electrical Specifi cation table shows parameter values of functionality and performance with the VIN C =140 μF, C =4 00 μF VOUT i o VIN VOUT C C GND i o GND +Sense -Sense PGOOD (SA1) SALERT CTRL Controller and digital interface VSET SYNC SCL SDA SA0 GCB VTRK PREF Fundamental Circuit Diagram www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 2 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Electrical Specifi cations, OKDY-T/50-W12-C and OKDH-T/50-W12-C TP1 = -30 to +95°C, VIN = 4.5 to 14 V, VIN > VOUT + 1.0 V Typical values given at: TP1 = +25 °C, VIN = 12.0 V, max IOUT, unless otherwise specifi ed under Conditions. Default confi guration fi le, 190 10-CDA 102 0206/001. External CIN = 470 μF/10 mΩ, COUT = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types. Sense pins are connected to the output pins. Characteristics Conditions Min Typ Max Unit V Input voltage rise time monotonic 2.4 V/ms I Output voltage without pin strap 1.2 V Output voltage adjustment range 0.60 3.3 V Output voltage adjustment including margining See Note 17 0.54 3.63 V Output voltage set-point resolution ±0.025% FS Including line, load, temp. -1 1 % See Note 14 Output voltage accuracy Current sharing operation -2 2 % See Note 15 Internal resistance +S/-S to VOUT/GND 47 Ω V O V = 0.6 V 2 O V = 1.0 V 2 O Line regulation mV V = 1.8 V 2 O V = 3.3 V 3 O V = 0.6 V 2 O V = 1.0 V 2 O Load regulation; I = 0 - 100% mV O V = 1.8 V 2 O V = 3.3 V 2 O V = 0.6 V 20 O V = 1.0 V 25 Output ripple & noise O V mVp-p Oac C = 470 μF (minimum external capacitance). See Note 11 V = 1.8 V 30 O O V = 3.3 V 35 O I Output current See Note 18 0.001 50 A O V = 0.6 V 3.10 O V = 1.0 V 4.80 O I Static input current at max I A S O V = 1.8 V 8.19 O V = 3.3 V 14.53 O I Current limit threshold 52 65 A lim V = 0.6 V 11 O V = 1.0 V 9 O I Short circuit current RMS, hiccup mode, See Note 3 A sc V = 1.8 V 7 O V = 3.3 V 6 O V = 0.6 V 85.6 O V = 1.0 V 90.4 O 50% of max I % O V = 1.8 V 93.7 O V = 3.3 V 95.7 O � Effi ciency V = 0.6 V 80.5 O V = 1.0 V 86.9 O max I % O V = 1.8 V 91.6 O V = 3.3 V 94.6 O V = 0.6 V 7.25 O V = 1.0 V 7.54 O P Power dissipation at max I W d O V = 1.8 V 8.28 O V = 3.3 V 9.36 O V = 0.6 V 0.90 O V = 1.0 V 0.90 Input idling power Default confi guration: Continues O P W li (no load) Conduction Mode, CCM V = 1.8 V 1.10 O V = 3.3 V 1.67 O www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 3 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit Default confi guration: Turned off with mW P Input standby power Monitoring enabled, 170 CTRL CTRL-pin Precise timing enabled C Internal input capacitance 140 μF i C Internal output capacitance400 μF o Total external output capacitance See Note 9 470 30 000 μF C ESR range of capacitors OUT See Note 9 5 30 mΩ (per single capacitor) Load transient peak V = 0.6 V 79 / 256 O Default confi guration voltage deviation V = 1.0 V 127 / 298 O di/dt = 2 A/μs V (L to H/H to L) mV tr1 V = 1.8 V 144 / 324 C = 470 μF (minimum external O O Load step 25-75-25% capacitance) see Note 12 V = 3.3 V 210 / 327 O of max I O Load transient recovery V = 0.6 V 60 / 100 O Default confi guration time, Note 5 V = 1.0 V 100 / 100 O di/dt = 2 A/μs t (L to H/H to L) μs tr1 V = 1.8 V 100 / 100 C = 470 μF (minimum external O O Load step 25-75-25% capacitance) see Note 12 V = 3.3 V 100 / 100 O of max I O Switching frequency 320 kHz f Switching frequency range PMBus confi gurable 200-640 kHz s Switching frequency set-point accuracy -5 5 % Control Circuit PWM Duty Cycle 5 95 % Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source -13 13 % UVLO threshold 3.85 V UVLO threshold range PMBus confi gurable 3.85-14 V Set point accuracy -150 150 mV Input Under Voltage Lockout, UVLO hysteresis 0.35 V UVLO UVLO hysteresis range PMBus confi gurable 0-10.15 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms IOVP threshold 16 V IOVP threshold range PMBus confi gurable 4.2-16 V Set point accuracy -150 150 mV Input Over Voltage Protection, IOVP hysteresis 1 V IOVP IOVP hysteresis range PMBus confi gurable 0-11.8 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms PG threshold 90 % V O PG hysteresis 5% V Power Good, PG, O See Note 2 PG delay See Note 19 Direct after DLC PG delay range PMBus confi gurable 0-500 s UVP threshold 85 % V O UVP threshold range PMBus confi gurable 0-100 % V O UVP hysteresis 5% V O Output voltage OVP threshold 115 % V O Over/Under Voltage Protection, OVP threshold range PMBus confi gurable 100-115 % V O OVP/UVP UVP/OVP response time25μs UVP/OVP PMBus confi gurable 5-60 μs response time range Fault response See Note 3 Automatic restart, 70 ms OCP threshold 62 A OCP threshold range PMBus confi gurable 0-62 A Over Current Protection, Protection delay, See Note 4 32 T sw OCP Protection delay range PMBus confi gurable 1-32 T sw Fault response See Note 3 Automatic restart, 70 ms www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 4 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit OTP threshold 120 °C OTP threshold range PMBus confi gurable -40…+125 °C Over Temperature Protection, OTP at P2 OTP hysteresis 25 °C See Note 8 OTP hysteresis range PMBus confi gurable 0-165 °C Fault response See Note 3 Automatic restart, 240 ms V Logic input low threshold SYNC, SA0, SA1, SCL, SDA, GCB, CTRL, 0.8 V IL V Logic input high threshold VSET 2 V IH I Logic input low sink current CTRL 0.6 mA IL V Logic output low signal level 0.4 V OL V Logic output high signal level 2.25 V OH SYNC, SCL, SDA, SALERT, GCB, PG I Logic output low sink current 4mA OL I Logic output high source current 2mA OH t Setup time, SMBus See Note 1 300 ns set t Hold time, SMBus See Note 1 250 ns hold t Bus free time, SMBus See Note 1 2 ms free C Internal capacitance on logic pins 10 pF p Initialization time See Note 10 40 ms Delay duration See Note 16 10 ms Delay duration range PMBus confi gurable 5-500000 Output Voltage Delay accuracy Delay Time -0.25/+4 ms turn-on See Note 6 Delay accuracy -0.25/+4 ms turn-off Ramp duration 10 ms Output Voltage Ramp duration range PMBus confi gurable 0-200 Ramp Time 100 μs See Note 13 Ramp time accuracy Current sharing operation 20 % VTRK Input Bias Current V = 5.5 V 110 200 μA VTRK 100% tracking, see Note 7 -100 100 mV Current sharing operation VTRK Tracking Ramp Accuracy (V - V ) O VTRK 2 phases, 100% tracking ±100 mV V = 1.0 V, 10 ms ramp O 100% Tracking -1 1 % VTRK Regulation Accuracy (V - V ) Current sharing operation O VTRK -2 2 % 100% Tracking Steady state operation Max 2 x READ_IOUT monitoring accuracy Current difference between products in a current sharing group Ramp-up 4 A Number of products in a current sharing group 7 READ_VIN vs V3 % I READ_VOUT vs V 1% O I = 0-50 A, T = 0 to +95 °C O P1 Monitoring accuracy READ_IOUT vs I ±3.0 A O V = 4.5-14 V, V = 1.0 V I O I = 0-50 A, T = 0 to +95 °C O P1 READ_IOUT vs I ±5.0 A O V = 4.5-14 V, V = 0.6-3.3 V I O 2 Note 1: See section I C/SMBus Setup and Hold Times – Defi nitions. Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. Note 2: Monitorable over PMBus Interface. Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the Note 13: Time for reaching 100% of nominal Vout. fault reappear after restart. See Operating Information for other fault response options. Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus. Note 4: Tsw is the switching period. Note 15: Accuracy here means deviation from ideal output voltage level given by confi gured droop and actual load. Note 5: Within +/-3% of VO Includes line, load and temperature variations. Note 6: See section Soft-start Power Up. Note 16: For current sharing the Output Voltage Delay Time must be reconfi gured to minimum 15 ms. Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative. accuracy will depend on the regulator bandwidth. Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). Note 8: See section Over Temperature Protection (OTP). Note 19: See sections Dynamic Loop Compensation and Power Good. Note 9: See section External Capacitors. Note 10: See section Initialization Procedure. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 5 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Efficiency and Power Dissipation Efficiency vs. Output Current, V = 5 V Power Dissipation vs. Output Current, V = 5 V I I [%] [W] 100 12 10 95 8 90 0.6 V 0.6 V 6 1.0 V 1.0 V 85 4 1.8 V 1.8 V 80 3.3 V 3.3 V 2 75 0 [A] [A] 00102030450 00102030450 Efficiency vs. load current and output voltage: Dissipated power vs. load current and output voltage: T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current, V = 12 V Power Dissipation vs. Output Current, V = 12 V I I [%] [W] 100 12 10 95 8 90 0.6 V 0.6 V 6 1.0 V 1.0 V 85 4 1.8 V 1.8 V 80 3.3 V 3.3 V 2 75 0 001020304 50 [A] 00102030450 [A] Efficiency vs. load current and output voltage at Dissipated power vs. load current and output voltage: T = +25 °C, V = 12 V, f = 320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V = 12 V, f = 320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current and Power Dissipation vs. Output Current and Switching Frequency Switching frequency [%] [W] 95 12 10 90 200 200 kHz kHz 8 85 320 320 kHz kHz 6 480 480 80 kHz kHz 4 640 640 75 kHz kHz 2 70 0 010 02 03 0450 001 02 030450 [A] [A] Efficiency vs. load current and switch frequency at Dissipated power vs. load current and switch frequency at T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ. T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ. P1 I O O P1 I O O Default configuration except changed frequency Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 6 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Load Transient Load Transient vs. External Capacitance, V = 1.0 V Load Transient vs. External Capacitance, V = 3.3 V O O [mV] [mV] 500 500 Universal PID, Universal PID, No NLR No NLR 400 400 DLC, DLC, No NLR No NLR Universal PID, Universal PID, 300 300 Default NLR Default NLR DLC, DLC, 200 200 Default NLR Default NLR Universal PID, Universal PID, 100 Opt. NLR 100 Opt. NLR DLC, DLC, Opt. NLR Opt. NLR 0 0 01234 5 [mF] 05 13 2 4 [mF] Load transient peak voltage deviation vs. external capacitance. Load transient peak voltage deviation vs. external capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mŸ, Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mŸ, T = +25 °C, V = 12 V, V = 1.0 V, f = 320 kHz, di/dt = 2 A/μs T = +25 °C, V = 12 V, V = 3.3 V, f = 320 kHz, di/dt = 2 A/μs P1 I O sw P1 I O sw Load transient vs. Switch Frequency Output Load Transient Response, Default Configuration [mV] 600 Universal PID, No NLR 500 DLC, No NLR 400 Universal PID, Default NLR 300 DLC, Default NLR 200 Universal PID, Opt. NLR 100 DLC, Opt. NLR 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Output voltage response to load current Top trace: output voltage (200 Step-change (12.5-37.5-12.5 A). Step-change (12.5-37.5-12.5 A) at: mV/div.). T = +25 °C. V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: load current (10 P1 I O O P1 I O di/dt = 2 A/μs, f = 320 kHz A/div.). sw C = 470 μF/10 mŸ Time scale: (0.1 ms/div.). O Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC). Note 2: In the load transient graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 7 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Current Characteristic Output Current Derating, V = 0.6 V Output Current Derating, V = 1.0 V O O [A] [A] 50 50 3.0 m/s 3.0 m/s 40 40 2.0 m/s 2.0 m/s 30 30 1.0 m/s 1.0 m/s 0.5 m/s 0.5 m/s 20 20 Nat. Conv. Nat. Conv. 10 10 0 0 20 40 60 80 100 120 20 40 60 80 100 120 [°C] [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 0.6 V, V = 12 V. See Thermal Consideration section. V = 1.0 V, V = 12 V. See Thermal Consideration section. O I O I Output Current Derating, V = 1.8 V Output Current Derating, V = 3.3 V O O [A] [A] 50 50 3.0 m/s 3.0 m/s 40 40 2.0 m/s 2.0 m/s 30 30 1.0 m/s 1.0 m/s 0.5 m/s 0.5 m/s 20 20 Nat. Conv. Nat. Conv. 10 10 0 0 20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 1.8 V, V = 12 V. See Thermal Consideration section. V = 3.3 V, V = 12 V. See Thermal Consideration section. O I O I Current Limit Characteristics, V = 1.0 V Current Limit Characteristics, V = 3.3 V O O [V] [V] 1.2 4.0 V = 4.5, 5 .0V I V = 5.0, 12 V I 0.9 3.0 4.5 V 4.5 V 5.0 V 5.0 V 0.6 2.0 12 V 12 V V = 4.5,14 V V = 12, 14 V I I 14 V 14 V 0.3 1.0 0.0 0.0 50 55 60 65 50 55 60 65 [A] [A] Output voltage vs. load current at T = +25 °C, V = 1.0 V. Output voltage vs. load current at T = +25 °C, V = 3.3 V. P1 O P1 O Note: Output enters hiccup mode at current limit. Note: Output enters hiccup mode at current limit. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 8 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Voltage Output Ripple & Noise, V = 1.0 V Output Ripple & Noise, V = 3.3 V O O Output voltage ripple at: T = +25 °C, Trace: output voltage (10 mV/div.). Output voltage ripple at: T = +25 °C, Trace: output voltage (10 mV/div.). P1 P1 V = 12 V, C = 470 μF/10 mŸ Time scale: (2 μs/div.). V = 12 V, C = 470 μF/10 mŸ Time scale: (2 μs/div.). I O I O I = 50 A I = 50 A O O Output Ripple vs. Input Voltage Output Ripple vs. Frequency [mV ] [mV ] pk-pk pk-pk 40 70 60 30 50 0.6 V 0.6 V 1.0 V 40 1.0 V 20 1.8 V 1.8 V 30 3.3 V 3.3 V 20 10 10 0 0 [V] [kHz] 59 7 11 13 200 300 400 500 600 Output voltage ripple V at: T = +25 °C, C = 470 μF/10 mŸ, I = 50 A Output voltage ripple V at: T = +25 °C, V = 12 V, C = 470 μF/10 mŸ, pk-pk P1 O O pk-pk P1 I O I = 50 A. Default configuration except changed frequency. O Output Ripple vs. External Capacitance Load regulation, V =1.0 V O [mV] [V] 40 1.010 30 1.005 0.6 V 4.5 V 1.0 V 5.0 V 20 1.000 12 V 1.8 V 14 V 3.3 V 10 0.995 0 0.990 03 12 4 5 0 5 10 15 20 25 [mF] [A] Output voltage ripple V at: T = +25 °C, V = 12 V. I = 50 A. Load regulation at V = 1.0 V, T = +25 °C, C = 470 μF/10 mŸ pk-pk P1 I O O P1 O Parallel coupling of capacitors with 470 μF/10 mŸ www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 9 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Start-up and shut-down Start-up by input source Shut-down by input source Start-up enabled by connecting V at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div.). I T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: input voltage (5 V/div.). V at: Bottom trace: input voltage (5 V/div.). P1 I O I C = 470 μF/10 mŸ, I = 50 A Time scale: (20 ms/div.). T = +25 °C, V = 12 V, V = 1.0 V Time scale: (2 ms/div.). O O P1 I O C = 470 μF/10 mŸ, I = 50 A O O Start-up by CTRL signal Shut-down by CTRL signal Start-up by enabling CTRL signal at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: CTRL signal (2 V/div.). V at: Bottom trace: CTRL signal (2 V/div.). P1 I O I C = 470 μF/10 mŸ, I = 50 A Time scale: (20 ms/div.). T = +25 °C, V = 12 V, V = 1.0 V Time scale: (2 ms/div.). O O P1 I O C = 470 μF/10 mŸ, I = 50 A O O www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 10 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Electrical Specifi cations, OKDX-T/50-W12-C T = -30 to +95 °C, V = 4.5 to 14 V, V > V + 1.0 V P1 I I O Typical values given at: T = +25 °C, V = 12.0 V, max I , unless otherwise specifi ed under Conditions. P1 I O Default confi guration fi le, 190 10-CDA 102 0259/001. External C = 470 μF/10 mΩ, C = 470 μF/10 mΩ. See Operating Information section for selection of capacitor types. IN OUT Sense pins are connected to the output pins. Characteristics Conditions Min Typ Max Unit V Input voltage rise time monotonic 2.4 V/ms I Output voltage without pin strap 1.2 V Output voltage adjustment range 0.60 3.3 V Output voltage adjustment including margining See Note 17 0.54 3.63 V Output voltage set-point resolution ±0.025 % FS Including line, load, temp. -1 1 % See Note 14 Output voltage accuracy Current sharing operation -2 2 % See Note 15 V Internal resistance +S/-S to VOUT/GND 47 Ω O V = 0.6 V 2 O V = 1.0 V 2 O Line regulation mV V = 1.8 V 2 O V = 3.3 V 3 O V = 0.6 V 2 O V = 1.0 V 2 O Load regulation; I = 0 - 100% mV O V = 1.8 V 2 O V = 3.3 V 2 O V = 0.6 V 20 O V = 1.0 V 25 Output ripple & noise O V mVp-p Oac C = 470 μF (minimum external capacitance). See Note 11 V = 1.8 V 30 O O V = 3.3 V 40 O I Output current See Note 18 0.001 50 A O V = 0.6 V 3.12 O V = 1.0 V 4.81 O I Static input current at max I A S O V = 1.8 V 8.22 O V = 3.3 V 14.59 O I Current limit threshold 52 65 A lim V = 0.6 V 10 O V = 1.0 V 8 O I Short circuit current RMS, hiccup mode, See Note 3 A sc V = 1.8 V 6 O V = 3.3 V 5 O V = 0.6 V 85.2 O V = 1.0 V 90.2 O 50% of max I % O V = 1.8 V 93.3 O V = 3.3 V 95.3 O � Effi ciency V = 0.6 V 80.2 O V = 1.0 V 86.6 O max I % O V = 1.8 V 91.2 O V = 3.3 V 94.2 O V = 0.6 V 7.40 O V = 1.0 V 7.73 O P Power dissipation at max I W d O V = 1.8 V 8.68 O V = 3.3 V 10.15 O V = 0.6 V 0.95 O Input idling power Default confi guration: Continues V = 1.0 V 0.95 O P W li (no load) Conduction Mode, CCM V = 1.8 V 1.22 O V = 3.3 V 1.88 O Default confi guration: Turned off with mW P Input standby power Monitoring enabled, 170 CTRL CTRL-pin Precise timing enabled C Internal input capacitance 140 μF i www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 11 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit C Internal output capacitance 400 μF o Total external output capacitance See Note 9 470 30 000 μF C ESR range of capacitors OUT See Note 9 5 30 mΩ (per single capacitor) V = 0.6 V 90 / 300 O Load transient peak Default confi guration voltage deviation V = 1.0 V 120 / 300 O di/dt = 2 A/μs V (L to H/H to L) mV tr1 C = 470 μF (minimum external O V = 1.8 V 160 / 305 Load step 25-75-25% O capacitance) see Note 12 of max I O V = 3.3 V 230 / 315 O V = 0.6 V 70 / 100 O Load transient recovery Default confi guration time, Note 5 V = 1.0 V 100 / 100 O di/dt = 2 A/μs t (L to H/H to L) μs tr1 C = 470 μF (minimum external O V = 1.8 V 100 / 100 Load step 25-75-25% O capacitance) see Note 12 of max I O V = 3.3 V 100 / 100 O Switching frequency 320 kHz f Switching frequency range PMBus confi gurable 200-640 kHz s Switching frequency set-point accuracy -5 5 % Control Circuit PWM Duty Cycle 5 95 % Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source -13 13 % UVLO threshold 3.85 V UVLO threshold range PMBus confi gurable 3.85-14 V Set point accuracy -150 150 mV Input Under Voltage Lockout, UVLO hysteresis 0.35 V UVLO UVLO hysteresis range PMBus confi gurable 0-10.15 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms IOVP threshold 16 V IOVP threshold range PMBus confi gurable 4.2-16 V Set point accuracy -150 150 mV Input Over Voltage Protection, IOVP hysteresis 1 V IOVP IOVP hysteresis range PMBus confi gurable 0-11.8 V Delay 2.5 μs Fault response See Note 3 Automatic restart, 70 ms PG threshold 90 % V O Power Good, PG, PG hysteresis 5% V O See Note 2 PG delay See Note 19 Direct after DLC ms PG delay range PMBus confi gurable 0-500 s UVP threshold 85 % V O UVP threshold range PMBus confi gurable 0-100 % V O UVP hysteresis 5% V O Output voltage OVP threshold 115 % V O Over/Under Voltage Protection, OVP threshold range PMBus confi gurable 100-115 % V O OVP/UVP UVP/OVP response time 25 μs UVP/OVP PMBus confi gurable 5-60 μs response time range Fault response See Note 3 Automatic restart, 70 ms OCP threshold 60 A OCP threshold range PMBus confi gurable 0-60 A Over Current Protection, Protection delay, See Note 4 32 T sw OCP Protection delay range PMBus confi gurable 1-32 T sw Fault response See Note 3 Automatic restart, 70 ms www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 12 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Characteristics Conditions Min Typ Max Unit OTP threshold 120 °C OTP threshold range PMBus confi gurable -40…+125 Over Temperature Protection, °C OTP at P2 OTP hysteresis 25 °C See Note 8 OTP hysteresis range PMBus confi gurable 0-165 °C Fault response See Note 3 Automatic restart, 240 ms V Logic input low threshold SYNC, SA0, SA1, SCL, SDA, GCB, CTRL, 0.8 V IL V Logic input high threshold VSET 2 V IH I Logic input low sink current CTRL 0.6 mA IL V Logic output low signal level 0.4 V OL V Logic output high signal level 2.25 V OH SYNC, SCL, SDA, SALERT, GCB, PG I Logic output low sink current 4mA OL I Logic output high source current 2mA OH t Setup time, SMBus See Note 1 300 ns set t Hold time, SMBus See Note 1 250 ns hold t Bus free time, SMBus See Note 1 2 ms free C Internal capacitance on logic pins 10 pF p Initialization time See Note 10 40 ms Delay duration See Note 16 10 ms Delay duration range PMBus confi gurable 5-500000 Output Voltage Delay accuracy Delay Time -0.25/+4 ms turn-on See Note 6 Delay accuracy -0.25/+4 ms turn-off Ramp duration 10 ms Output Voltage Ramp duration range PMBus confi gurable 0-200 Ramp Time 100 μs See Note 13 Ramp time accuracy Current sharing operation 20 % VTRK Input Bias Current V = 5.5 V 110 200 μA VTRK 100% tracking, see Note 7 -100 100 mV Current sharing operation VTRK Tracking Ramp Accuracy (V - V ) O VTRK 2 phases, 100% tracking ±100 mV V = 1.0 V, 10 ms ramp O 100% Tracking -1 1 % VTRK Regulation Accuracy (V - V ) Current sharing operation O VTRK -2 2 % 100% Tracking Steady state operation Max 2 x READ_IOUT monitoring accuracy Current difference between products in a current sharing group Ramp-up 4 A Number of products in a current sharing group 7 READ_VIN vs V 3% I READ_VOUT vs V 1% O I = 0-50 A, T = 0 to +95 °C O P1 Monitoring accuracy READ_IOUT vs I ±3.0 A O V = 4.5-14 V, V = 1.0 V I O I = 0-50 A, T = 0 to +95 °C O P1 READ_IOUT vs I ±5.0 A O V = 4.5-14 V, V = 0.6-3.3 V I O 2 Note 1: See section I C/SMBus Setup and Hold Times – Defi nitions. Note 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. Note 2: Monitorable over PMBus Interface. Note 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. Note 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the Note 13: Time for reaching 100% of nominal Vout. fault reappear after restart. See Operating Information for other fault response options. Note 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus. Note 4: Tsw is the switching period. Note 15: Accuracy here means deviation from ideal output voltage level given by confi gured droop and actual load. Note 5: Within +/-3% of VO Includes line, load and temperature variations. Note 6: See section Soft-start Power Up. Note 16: For current sharing the Output Voltage Delay Time must be reconfi gured to minimum 15 ms. Note 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals Note 17: For steady state operation above 1.05 x 3.3 V, please contact your local Murata sales representative. accuracy will depend on the regulator bandwidth. Note 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). Note 8: See section Over Temperature Protection (OTP). Note 19: See sections Dynamic Loop Compensation and Power Good. Note 9: See section External Capacitors. Note 10: See section Initialization Procedure. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 13 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Efficiency and Power Dissipation Efficiency vs. Output Current, V = 5 V Power Dissipation vs. Output Current, V = 5 V I I [%] [W] 100 12 10 95 8 90 0.6 V 0.6 V 6 1.0 V 1.0 V 85 4 1.8 V 1.8 V 80 3.3 V 3.3 V 2 75 0 [A] [A] 0 1020304050 0 10203040 50 Efficiency vs. load current and output voltage: Dissipated power vs. load current and output voltage: T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V = 5 V, f = 320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current, V = 12 V Power Dissipation vs. Output Current, V = 12 V I I [%] [W] 100 12 10 95 8 90 0.6 V 0.6 V 6 1.0 V 1.0 V 85 4 1.8 V 1.8 V 80 3.3 V 3.3 V 2 75 0 [A] [A] 0 1020304050 0 10 2030 4050 Efficiency vs. load current and output voltage at Dissipated power vs. load current and output voltage: T = +25 °C, V =12 V, f = 320 kHz, C = 470 μF/10 mŸ. T = +25 °C, V =12 V, f = 320 kHz, C = 470 μF/10 mŸ. P1 I sw O P1 I sw O Efficiency vs. Output Current and Power Dissipation vs. Output Current and Switching Frequency Switching frequency [%] [W] 95 12 10 90 200 200 kHz kHz 8 85 320 320 kHz kHz 6 480 480 80 kHz kHz 4 640 640 75 kHz kHz 2 70 0 0 1020304050 0 10203040 50 [A] [A] Efficiency vs. load current and switch frequency at Dissipated power vs. load current and switch frequency at T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ. T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ. P1 I O O P1 I O O Default configuration except changed frequency Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 14 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Load Transient Load Transient vs. External Capacitance, V = 1.0 V Load Transient vs. External Capacitance, V = 3.3 V O O [mV] [mV] 500 500 Universal PID, Universal PID, No NLR No NLR 400 400 DLC, DLC, No NLR No NLR Universal PID, Universal PID, 300 300 Default NLR Default NLR DLC, DLC, 200 200 Default NLR Default NLR Universal PID, Universal PID, 100 Opt. NLR 100 Opt. NLR DLC, DLC, Opt. NLR Opt. NLR 0 0 01234 5 012345 [mF] [mF] Load transient peak voltage deviation vs. external capacitance. Load transient peak voltage deviation vs. external capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mŸ, Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mŸ, T = +25 °C. V = 12 V, V = 1.0 V, f = 320 kHz, di/dt = 2 A/μs T = +25 °C. V = 12 V, V = 3.3 V, f = 320 kHz, di/dt = 2 A/μs P1 I O sw P1 I O sw Load transient vs. Switch Frequency Output Load Transient Response, Default Configuration [mV] 600 Universal PID, No NLR 500 DLC, No NLR 400 Universal PID, Default NLR 300 DLC, Default NLR 200 Universal PID, Opt. NLR 100 DLC, Opt. NLR 0 200 300 400 500 600 [kHz] Load transient peak voltage deviation vs. frequency. Output voltage response to load Top trace: output voltage (200 mV/div.). Step-change (12.5-37.5-12.5 A). Step-change (12.5-37.5-12.5 A) at: Bottom trace: load current (10 A/div.). T = +25 °C. V = 12 V, V = 1.0 V, C = 470 μF/10 mŸ T = +25 °C, V = 12 V, V = 1.0 V Time scale: (0.1 ms/div.). P1 I O O P1 I O di/dt = 2 A/μs, f = 320 kHz sw C = 470 μF/10 mŸ O Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC). Note 2: In these graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 15 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Current Characteristic Output Current Derating, V = 0.6 V Output Current Derating, V = 1.0 V O O [A] [A] 50 50 3.0 m/s 3.0 m/s 40 40 2.0 m/s 2.0 m/s 1.0 m/s 30 30 1.0 m/s 0.5 m/s 0.5 m/s 20 20 Nat. Conv. Nat. Conv. 10 10 0 0 20 40 60 80 100 120 20 40 60 80 100 120 [°C] [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 0.6 V, V = 12 V. See Thermal Consideration section. V = 1.0 V, V = 12 V. See Thermal Consideration section. O I O I Output Current Derating, V = 1.8 V Output Current Derating, V = 3.3 V O O [A] [A] 50 50 3.0 m/s 3.0 m/s 40 40 2.0 m/s 2.0 m/s 30 30 1.0 m/s 1.0 m/s 0.5 m/s 0.5 m/s 20 20 Nat. Conv. Nat. Conv. 10 10 0 0 20 40 60 80 100 120 20 40 60 80 100 120 [°C] [°C] Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at V = 1.8 V, V = 12 V. See Thermal Consideration section. V = 3.3 V, V = 12 V. See Thermal Consideration section. O I O I Current Limit Characteristics, V = 1.0 V Current Limit Characteristics, V = 3.3 V O O [V] [V] 1,2 4,0 0,9 3,0 4.5 V 4.5 V 5.0 V 5.0 V 0,6 2,0 12 V V = 4.5, 5.0 V V =12, 14 V I 12 V V = 4.5, 14 V V = 5.0, 12 V I I I 14 V 14 V 0,3 1,0 0,0 0,0 50 55 60 65 50 55 60 65 [A] [A] Output voltage vs. load current at T = +25 °C, V = 1.0 V. Output voltage vs. load current at T = +25 °C, V = 3.3 V. P1 O P1 O Note: Output enters hiccup mode at current limit. Note: Output enters hiccup mode at current limit. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 16 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Output Voltage Output Ripple & Noise, V = 1.0 V Output Ripple & Noise, V = 3.3 V O O Output voltage ripple at: T = +25 °C, Trace: output voltage (10 mV/div.). Output voltage ripple at: T = +25 °C, Trace: output voltage (10 mV/div.). P1 P1 V = 12 V, C = 470 μF/10 mŸ Time scale: (2 μs/div.). V = 12 V, C = 470 μF/10 mŸ Time scale: (2 μs/div.). I O I O I = 50 A I = 50 A O O Output Ripple vs. Input Voltage Output Ripple vs. Frequency [mV ] [mV ] pk-pk pk-pk 50 60 50 40 0.6 V 0.6 V 40 30 1.0 V 1.0 V 30 1.8 V 1.8 V 20 3.3 V 20 3.3 V 10 10 0 0 [V] [kHz] 579 11 13 200 300 400 500 600 Output voltage ripple V at: T = +25 °C, C = 470 μF/10 mŸ, I = 50 A. Output voltage ripple V at: T = +25 °C, V = 12 V, C = 470 μF/10 mŸ, pk-pk P1 O O pk-pk P1 I O I = 50 A. Default configuration except changed frequency. O Output Ripple vs. External Capacitance Load regulation, V = 1.0 V O [mV] [V] 50 1,010 40 1,005 0.6 V 4.5 V 30 1.0 V 5.0 V 1,000 12 V 1.8 V 20 14 V 3.3 V 0,995 10 0 0,990 012345 [mF] 0 5 10 15 20 25 [A] Output voltage ripple V at: T = +25 °C, V = 12 V, I = 50 A. Load regulation at V = 1.0 V, T = +25 °C, C = 470 μF/10 mŸ pk-pk P1 I O O P1 O Parallel coupling of capacitors with 470 μF/10 mŸ www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 17 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Characteristics Start-up and shut-down Start-up by input source Shut-down by input source Start-up enabled by connecting V at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). I T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: input voltage (5 V/div.). V at: Bottom trace: input voltage (5 V/div.). P1 I O I C = 470 μF/10 mŸ, I = 50 A Time scale: (20 ms/div.). T = +25 °C, V = 12 V, V = 1.0 V Time scale: (2 ms/div.). O O P1 I O C = 470 μF/10 mŸ, I = 50 A O O Start-up by CTRL signal Shut-down by CTRL signal Start-up by enabling CTRL signal at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). T = +25 °C, V = 12 V, V = 1.0 V Bottom trace: CTRL signal (2 V/div.). V at: Bottom trace: CTRL signal (2 V/div.). P1 I O I C = 470 μF/10 mŸ, I = 50 A Time scale: (20 ms/div.). T = +25 °C, V = 12 V, V = 1.0 V Time scale: (2 ms/div.). O O P1 I O C = 470 μF/10 mŸ, I = 50 A O O www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 18 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series EMC Specifi cation Output Ripple and Noise Conducted EMI measured according to test set-up below. The funda- Output ripple and noise is measured according to fi gure below. mental switching frequency is 320 kHz at VI = 12 V, max IO. A 50 mm conductor works as a small inductor forming together with the two capacitors as a damped fi lter. Conducted EMI Input terminal value (typical for default confi guration) 50 mm conductor Vout Tantalum Ceramic Capacitor Capacitor +S Output 10 μF 0.1 μF Capacitor 470 μF/10 m Ω –S GND 50 mm conductor BNC-contact to oscilloscope Output ripple and noise test set-up. Operating information Power Management Overview This product is equipped with a PMBus interface. The product incorpo- EMI without fi lter rates a wide range of readable and confi gurable power management features that are simple to implement with a minimum of external To spectrum analyzer components. Additionally, the product includes protection features that continuously safeguard the load from damage due to unexpected system faults. A fault is also shown as an alert on the SALERT pin. RF Current probe The following product parameters can continuously be monitored by a 1kHz – 50MHz Resistive Battery host: Input voltage, output voltage/current, and internal temperature. If load supply the monitoring is not needed it can be disabled and the product enters a low power mode reducing the power consumption. The protection C1 features are not affected. POL The product is delivered with a default confi guration suitable for a wide range operation in terms of input voltage, output volt- 50mm age, and load. The confi guration is stored in an internal Non-Volatile Memory (NVM). All power management functions can be reconfi gured C1 = 10uF / 600VDC Feed- Thru RF capacitor using the PMBus interface. Please contact your local Murata Power Solutions representative for design support of custom confi gura- 200mm tions or appropriate SW tools for design and download of your own 800mm confi gurations. Conducted EMI test set-up Input Voltage Layout Recommendations The input voltage range, 4.5 - 14 V, makes the product easy to use in intermediate bus applications when powered by a non-regulated bus The radiated EMI performance of the product will depend on the PWB converter or a regulated bus converter. See Ordering Information for layout and ground layer design. It is also important to consider the stand- input voltage range. off of the product. If a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. A ground layer will increase the stray capacitance in the PWB and improve the high frequency EMC performance. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 19 of 41 Load OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Input Under Voltage Lockout, UVLO I =I D (1–D), inputRMS load The product monitors the input voltage and will turn-on and turn-off at configured levels. The default turn-on input voltage level setting is 4.20 V, where I is the output load current and D is the duty cycle. The load whereas the corresponding turn-off input voltage level is 3.85 V. Hence, I 2 maximum load ripple current becomes . The ripple current is the default hys
teresis between turn-on and turn-off input voltage is 0.35 V. load Once an input turn-off condition occurs, the device can respond in a divided into three parts, i.e., currents in the input source, external input number of ways as follows: capacitor, and internal input capacitor. How the current is divided depends on the impedance of the input source, ESR and capacitance values in the 1. Continue operating without interruption. The unit will continue to capacitors. A minimum capacitance of 300 μF with low ESR is operate as long as the input voltage can be supported. If the input recommended. The ripple current rating of the capacitors must follow voltage continues to fall, there will come a point where the unit will Eq. 1. For high-performance/transient applications or wherever the input cease to operate. source performance is degraded, additional low ESR ceramic type capacitors at the input is recommended. The additional input low ESR 2. Continue operating for a given delay period, followed by shutdown if capacitance above the minimum level insures an optimized performance. the fault still exists. The device will remain in shutdown until instructed to restart. Output capacitors: 3. Initiate an immediate shutdown until the fault has been cleared. The When powering loads with significant dynamic current requirements, the user can select a specific number of retry attempts. voltage regulation at the point of load can be improved by addition of decoupling capacitors at the load. The default response from a turn-off is an immediate shutdown of the The most effective technique is to locate low ESR ceramic and electrolytic device. The device will continuously check for the presence of the fault capacitors as close to the load as possible, using several capacitors in condition. If the fault condition is no longer present, the product will be re- parallel to lower the effective ESR. The ceramic capacitors will handle high- enabled. The turn-on and turn-off levels and response can be reconfigured frequency dynamic load changes while the electrolytic capacitors are used using the PMBus interface. to handle low frequency dynamic load changes. Ceramic capacitors will also reduce high frequency noise at the load. Remote Control It is equally important to use low resistance and low inductance PWB The product is equipped with a remote layouts and cabling. control function, i.e., the CTRL pin. The Vext External decoupling capacitors are a part of the control loop of the product remote control can be connected to and may affect the stability margins. either the primary negative input Stable operation is guaranteed for the following total capacitance C in O connection (GND) or an external CTRL the output decoupling capacitor bank where voltage (Vext), which is a 3 - 5 V positive supply voltage in accordance Eq. 2. μF. C >@ C ,C >470, 30000@ O min max GND to the SMBus Specification version The decoupling capacitor bank should consist of capacitors which has a 2.0. capacitance value larger than and has an ESR range of C tC min The CTRL function allows the product to be turned on/off by an external device like a semiconductor or mechanical switch. By default the product Eq. 3. mΩ ESR >@ ESR , ESR >5, 30@ min max will turn on when the CTRL pin is left open and turn off when the CTRL pin is applied to GND. The CTRL pin has an internal pull-up resistor. When the The control loop stability margins are limited by the minimum time constant CTRL pin is left open, the voltage generated on the CTRL pin is max 5.5 V. W of the capacitors. Hence, the time constant of the capacitors should min If the device is to be synchronized to an external clock source, the clock follow Eq. 4. frequency must be stable prior to asserting the CTRL pin. The product can also be configured using the PMBus interface to be Eq. 4. W tW C ESR 2.35 P s min min min “Always on ” or turn on/off can be performed with PMBus commands. This relation can be used if your preferred capacitors have parameters outside the above stated ranges in Eq. 2 and Eq.3. Input and Output Impedance The impedance of both the input source and the load will interact with the impedance of the product. It is important that the input source has low characteristic impedance. The performance in some applications can be enhanced by addition of external capacitance as described under External x If the capacitors capacitance value is C C one must use at least min Decoupling Capacitors. If the input voltage source contains significant N capacitors where inductance, the addition a capacitor with low ESR at the input of the C product will ensure stable operation. ªC º min min and ESRtESR . N t min « » C C « » External Capacitors x If the ESR value is ESR!ESR one must use at least N capacitors max Input capacitors: of that type where The input ripple RMS current in a buck converter is equal to www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 20 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series ª ESR º C min N t and Ct . « » The DLC can also be configured with Auto Comp Gain Control. This scales ESR N « max» the DLC results to allow a trade-off between transient response and x If the ESR value is ESR  ESR the capacitance value should be steady-state duty cycle jitter. A setting of 100% will provide the fastest min transient response while a setting of 10% will produce the lowest jitter. ESR min CtC . The default is 50%. min ESR For a total capacitance outside the above stated range or capacitors that do
Changing DLC and PID Setting not follow the stated above requirements above a re-design of the control Some caution must be considered while DLC is enabled and when it is loop parameters will be necessary for robust dynamic operation and changed from enabled or disabled. stability. When operating, the controller IC uses the settings loaded in its (volatile) RAM memory. When the input power is applied the RAM settings are Control Loop retrieved from the pin-strap resistors and the two non-volatile memories The product uses a voltage-mode synchronous buck controller with a fixed (DEFAULT and USER). The sequence is described in the “Initialization frequency PWM scheme. Although the product uses a digital control loop, it Procedure” section. operates much like a traditional analog PWM controller. As in the analog controller case, the control loop compares the output voltage to the desired When DLC is enabled: voltage reference and compensation is added to keep the loop stable and When DLC is enabled, the normal sequence (after input power has been fast. The resulting error signal is used to drive the PWM logic. Instead of applied) that a value stored in the user non-volatile memory overwrites any using external resistors and capacitors required with traditional analog previously loaded value does not apply for the PID setting (stored in the control loops, the product uses a digital Proportional-Integral-Derivative PID_TAPS register). The PID setting in the user non-volatile memory is (PID) compensator in the control loop. The characteristics of the control ignored and a non-configurable default PID setting is loaded to RAM to act loop is configured by setting PID compensation parameters. These PID as a safe starting value for the DLC. Once the output has been enabled and settings can be reconfigured using the PMBus interface. the DLC algorithm has found a new optimized PID setting, it will be loaded in RAM and used by the control loop. Dynamic Loop Compensation (DLC) The DLC feature might in some documents be referred to as “Auto When saving changes to the user non-volatile memory, all changes made to the content of RAM will be saved. This also includes the default PID Compensation” or “Auto Tuning” feature. setting (loaded to RAM to act as a safe starting value) or the PID setting The DLC feature measures the characteristics of the power train and changed by the DLC algorithm after enabling output. The result is that as calculates the proper compensator PID coefficients. long as DLC is enabled the PID setting in the user non-volatile memory is The default configuration is that once the output voltage ramp up has ignored, but it might accidentally get overwritten. completed, the DLC algorithm will begin and a new optimized compensator solution (PID setting) will be found and implemented. The When changing DLC from disabled to enabled: DLC algorithm typically takes between 50 ms and 200 ms to complete. A non-configurable default PID setting is loaded to RAM to act as a safe By the PMBus command AUTO_COMP_CONFIG the user may select starting value for the DLC (same as above). between several different modes of operation: When changing DLC from enabled to disabled: x Disable When changing DLC from enabled to disabled, the PID setting in the user x Autocomp once, will run DLC algorithm each time the output is non-volatile memory will be loaded to RAM. Any new optimized PID setting enabled (default configuration) in RAM will be lost, if not first stored to the user non-volatile memory. x Autocomp every second will initiate a new DLC algorithm each 1 second When DLC is disabled: x Autocomp every minute will initiate a new DLC algorithm every When DLC is disabled and input power has been applied, the PID setting in minute. the user non-volatile memory will be loaded to RAM and used in the control loop. The DLC can also be configured to run once only after the first ramp up The original PID setting in the user non-volatile memory is quite slow and (after input power have been applied) and to use that temporary stored PID not recommended for optimal performance. If DLC is disabled it is settings in all subsequent ramps. If input power is cycled a new DLC recommended to either: algorithm will be performed after the first ramp up. The default setting is 1. Use the DLC to find optimized PID setting. however to run the DLC algorithm after every ramp up. 2. Use Ericsson Power Designer to find appropriate PID setting. The DLC algorithm can also be initiated manually by sending the 3. Use Universal PID as defined below. AUTO_COMP_CONTROL command. The Universal PID setting (taps) is: www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 21 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series A = 3289.56, V [V] R [kΩ] V [V] R [kΩ] O SET O SET 0.60 10 1.50 46.4 B = -6248.12, 0.65 11 1.60 51.1 12.1 1.70 56.2 0.70 C = 2964.06 0.75 13.3 1.80 61.9 0.80 14.7 1.90 68.1 Write 0x7CB941FDC3417CCD99 to PID_TAPS register and write 0.85 16.2 2.00 75 command STORE_USER_ALL 0.90 17.8 2.10 82.5 Note that if DLC is enabled, for best results VI must be stable before 19.6 2.20 90.9 0.95 DLC algorithm begins. 1.00 21.5 2.30 100 23.7 2.50 110 1.05 Load Transient Response Optimization 1.10 26.1 3.00 121 The product incorporates a Non-Linear transient Response, NLR, loop 1.15 28.7 3.30 133 that decreases the response time and the output voltage deviation 1.20 31.6 during a load transient. The NLR results in a higher equivalent loop 1.25 34.8 1.30 bandwidth than is possible using a traditional linear control loop. The 38.3 1.40 42.2 product is pre-confi gured with appropriate NLR settings for robust and stable operation for a wide range of input voltage and a capacitive The output voltage and the maximum output voltage can be pin load range as defi ned in the section External Decoupling Capacitors. strapped to three fi xed values by connecting the VSET pin according For an application with a specifi c input voltage, output voltage, and to the table below. capacitive load, the NLR confi guration can be optimized for a robust V [V] VSET O and stable operation and with an improved load transient response. 0.60 Shorted to PREF 1.2 Open “high impedance” This will also reduce the amount of output decoupling capacitors and 2.5 Logic High, GND as reference yield a reduced cost. However, the NLR slightly reduces the effi - ciency. In order to obtain maximal energy effi ciency the load transient Output Voltage Adjust using PMBus requirement has to be met by the standard control loop compensation The output voltage set by pin-strap can be overridden by confi guration and the decoupling capacitors. The NLR settings can be reconfi gured fi le or by using a PMBus command. See Electrical Specifi cation for using the PMBus interface. adjustment range. Remote Sense When setting the output voltage by confi guration fi le or by a PMBus The product has remote sense that can be used to compensate for command, the specifi ed output voltage accuracy is valid only when voltage drops between the output and the point of load. The sense the set output voltage level falls within the same bin range as the traces should be located close to the PWB ground layer to reduce voltage level defi ned by the pin-strap resistor RSET. The applicable bin noise susceptibility. Due to derating of internal output capacitance ranges are defi ned in the table below. Valid accuracy for voltage levels the voltage drop should be kept below V = (5.5–V )/2. A large outside the applicable bin range is two times the specifi ed. DROPMAX O voltage drop will impact the electrical performance of the regulator. If Example: the remote sense is not needed, +S should be connected to VOUT and Nominal VO is set to 1.10 V by RSET = 26.1 kΩ. 1.10 V falls within the −S should be connected to GND. bin range 0.988-1.383 V, thus specifi ed accuracy is valid when adjust- Output Voltage Adjust using Pin-strap Resistor ing VO within 0.988-1.383V. Using an external Pin-strap resis- V bin ranges [V] O tor, RSET, the output voltage can 0.600 – 0.988 VSET be set in the range 0.6 V to 3.3 0.988 – 1.383 1.383 – 1.975 V at 28 different levels shown R SET 1.975 – 2.398 in the table below. The resistor PREF 2.398 – 2.963 should be applied between the 2.963 – 3.753 VSET pin and the PREF pin. Output Voltage Range Limitation RSET also sets the maximum output voltage, see section “Output The output voltage range that is possible to set by confi guration or Voltage Range Limitation.” The resistor is sensed only during product by the PMBus interface is limited by the pin-strap resistor RSET. The start-up. Changing the resistor value during normal operation will maximum output voltage is set to 110% of the nominal output value not change the output voltage. The input voltage must be at least 1 defi ned by RSET, V = 1.1 x V . This protects the load from an O,MAX O,RSET V larger than the output voltage in order to deliver the correct output over voltage due to an accidental wrong PMBus command. voltage. See Ordering Information for output voltage range. The following table shows recommended resistor values for RSET. Maximum 1% tolerance resistors are required. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 22 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Output Voltage Adjust Limitation using PMBus falls below 85% of the nominal voltage. These limits may be changed via the PMBus interface. A PG delay period is defi ned as the time from In addition to the maximum output voltage limitation by the pin-strap when all conditions within the product for asserting PG are met to resistor RSET, there is also a limitation in how much the output volt- when the PG signal is actually asserted. The default PG delay is set to age can be increased while the output is enabled. If output is disabled 10 ms. This value can be reconfi gured using the PMBus interface. then RSET resistor is the only limitation. For products with DLC the PG signal is by default asserted directly Example: after the DLC operation have been completed. If DLC is disabled the If the output is enabled with output voltage set to 1.0 V, then it is only confi gured PG delay will be used. This can be reconfi gured using the possible to adjust/change the output voltage up to 1.7- V as long as PMBus interface. the output is enabled. V setting V set range O O Switching Frequency when enabled [V] while enabled [V] The fundamental switching frequency is 320 kHz, which yields 0.000 – 0.988 ~0.2 to >1.2 optimal power effi ciency. The switching frequency can be set to any 0.988 – 1.383 ~0.2 to >1.7 1.383 – 1.975 ~0.2 to >2.5 value between 200 kHz and 640 kHz using the PMBus interface. The 1.975 – 2.398 ~0.2 to >2.97 switching frequency will change the effi ciency/power dissipation, 2.398 – 2.963 ~0.2 to >3.68 load transient response and output ripple. For optimal control loop 2.963 – 3.753 ~0.2 to >4.65 performance in a product without DLC, the control loop must be re- Over Voltage Protection (OVP) optimized when changing the switching frequency. The product includes over voltage limiting circuitry for protection Synchronization of the load. The default OVP limit is 15% above the nominal output Synchronization is a feature that allows multiple products to be syn- voltage. If the output voltage exceeds the OVP limit, the product can chronized to a common frequency. Synchronized products powered respond in different ways: from the same bus eliminate beat frequencies refl ected back to the 1. Initiate an immediate shutdown until the fault has been cleared. input supply, and also reduces EMI fi ltering requirements. Eliminating The user can select a specifi c number of retry attempts. the slow beat frequencies (usually <10 kHz) allows the EMI fi lter to be 2. Turn off the high-side MOSFET and turn on the low-side MOSFET. designed to attenuate only the synchronization frequency. Synchroni- The low-side MOSFET remains ON until the device attempts a zation can also be utilized for phase spreading, described in section restart, i.e. the output voltage is pulled to ground level (crowbar Phase Spreading. function). The products can be synchronized with an external oscillator or one The default response from an overvoltage fault is to immediately product can be confi gured with the SYNC pin as a SYNC Output work- shut down as in 2. The device will continuously check for the pres- ing as a master driving the synchronization. All others on the same ence of the fault condition, and when the fault condition no longer synchronization bus must be confi gured with SYNC Input. Default exists the device will be re-enabled. For continuous OVP when confi guration is using the internal clock, independently of signal at the operating from an external clock for synchronization, the only allowed SYNC pin. response is an immediate shutdown. The OVP limit and fault response Phase Spreading can be reconfi gured using the PMBus interface. When multiple products share a common DC input supply, spreading Under Voltage Protection (UVP) of the switching clock phase between the products can be utilized. The product includes output under voltage limiting circuitry for This dramatically reduces input capacitance requirements and effi - protection of the load. The default UVP limit is 15% below the nominal ciency losses, since the peak current drawn from the input supply is output voltage. The UVP limit can be reconfi gured using the PMBus effectively spread out over the whole switch period. This requires that interface. the products are synchronized. Up to 16 different phases can be used. Power Good The phase spreading of the product can be confi gured using the PMBus interface. The product provides a Power Good (PG) fl ag in the Status Word reg- ister that indicates the output voltage is within a specifi ed tolerance Parallel Operation (Current Sharing) of its target level and no fault condition exists. If specifi ed in section Paralleling multiple products can be used to increase the output cur- Connections, the product also provides a PG signal output. The PG pin rent capability of a single power rail. By connecting the GCB pins of is active high and by default open-drain but may also be confi gured each device and confi guring the devices as a current sharing rail, the as push-pull via the PMBus interface. units will share the current equally, enabling up to 100% utilization of By default, the PG signal will be asserted when the output reaches the current capability for each device in the current sharing rail. The above 90% of the nominal voltage, and de-asserted when the output product uses a low-bandwidth, fi rst-order digital current sharing by www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 23 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series aligning the output voltage of the slave devices to deliver the same shutdown of the device. The device will continuously check for the current as the master device. Artifi cial droop resistance is added to presence of the fault condition, and if the fault condition no longer the output voltage path to control the slope of the load line curve, exists the device will be re-enabled. The load distribution should be calibrating out the physical parasitic mismatches due to power train designed for the maximum output short circuit current specifi ed. The components and PWB layout. Up to 7 devices can be confi gured in a OCP limit and response of the product can be reconfi gured using the given current sharing group. PMBus interface. In order to avoid interference with other algorithms executing Initialization Procedure during parallel operation, the dead-time algorithm should be turned The product follows a specifi c internal initialization procedure after off and fi xed dead-times be used. power is applied to the VIN pin: 1. Status of the address and output voltage pin-strap pins are checked Phase Adding and Shedding for Parallel Operation and values associated with the pin settings are loaded to RAM. During periods of light loading, it may be benefi cial to disable one or more phases (modules) in order to eliminate the current drain and 2. Values stored in the Murata default non-volatile memory are switching losses associated with those phases, resulting in higher loaded to RAM. This overwrites any previously loaded values. effi ciency. The product offers the ability to add and drop phases 3. Values stored in the user non-volatile memory are loaded to RAM. (modules) using a PMBus command in response to an observed This overwrites any previously loaded values. load current change. All phases (modules) in a current share rail are considered active prior to the current sharing rail ramp to power-good. Once the initialization process is completed, the product is ready Phases can be dropped after power-good is reached. Any member to be enabled using the CTRL pin. The product is also ready to accept of the current sharing rail can be dropped. If the reference module is commands via the PMBus interface, which will overwrite any values dropped, the remaining active module with the lowest member posi- loaded during the initialization procedure. tion will become the new reference. Additionally, any change to the Soft-start Power Up number of members of a current sharing rail will precipitate autono- The soft-start control introduces a time-delay before allowing the mous phase distribution within the rail where all active phases realign output voltage to rise. Once the initialization time has passed the their phase position based on their order within the number of active device will wait for the confi gured delay period prior to starting to members. If the members of a current sharing rail are forced to shut ramp its output. After the delay period has expired, the output will down due to an observed fault, all members of the rail will attempt to begin to ramp towards its target voltage according to the confi gured re-start simultaneously after the fault has cleared. soft-start ramp time. Effi ciency Optimized Dead Time Control The default settings for the soft-start delay period and the soft- The product utilizes a closed loop algorithm to optimize the dead- start ramp time is 10 ms. Hence, power-up is completed within 20 time applied between the gate drive signals for the switch and synch ms in default confi guration using remote control. When the soft-start FETs. The algorithm constantly adjusts the deadtime non-overlap to delay time is set to 0 ms, the module will begin its ramp-up after the minimize the duty cycle, thus maximizing effi ciency. This algorithm internal circuitry has initialized (approximately 2 ms). It is generally will null out deadtime differences due to component variation, tem- recommended to set the soft-start ramp-up time to a value greater perature and loading effects. The algorithm can be confi gured via the than 500 μs to prevent inadvertent fault conditions due to excessive PMBus interface. inrush current. The acctual minimum ramp-up time will however normally be limited by the control loop settings and ramp-up times of Over Current Protection (OCP) internal interface voltages in the controller circuit to approximately 2 The product includes current limiting circuitry for protection at con- ms. The soft-start power up of the product can be reconfi gured using tinuous overload. The following OCP response options are available: the PMBus interface. 1. Initiate a shutdown and attempt to restart an infi nite number of times with a preset delay period between attempts. 2. Initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. VIN 3. Continue operating for a given delay period, followed by shutdown if the fault still exists. CTRL 4. Continue operating through the fault (this could result in perma- VOUT nent damage to the power supply). Initialization Delay Ramp 5. Initiate an immediate shutdown. time time time The default response from an over current fault is an immediate Illustration of Power Up Procedure www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 24 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series VOUT VOUT V1 MASTER V2 SLAVE t t Illustration of Output Voltage Sequencing. Illustration of Ratiometric Voltage Tracking The master device in a tracking group is defi ned as the device Output Voltage Sequencing that has the highest target output voltage within the group. This A group of products may be confi gured to power up in a predeter- master device will control the ramp rate of all tracking devices and is mined sequence. This feature is especially useful when powering not confi gured for tracking mode. All of the CTRL pins in the track- advanced processors, FPGAs, and ASICs that require one supply to ing group must be connected and driven by a single logic source. It reach its operating voltage prior to another. Multi-product sequenc- should be noted that current sharing groups that are also confi gured ing can be achieved by confi guring the start delay and rise time of to track another voltage do not offer pre-bias protection; a minimum each device through the PMBus interface and by using the CTRL start load should therefore be enforced to avoid the output voltage from signal. being held up by an outside force. Voltage Tracking Voltage Margining Up/Down The product integrates a lossless tracking scheme that allows its The product can adjust its output higher or lower than its nominal output to track a voltage that is applied to the VTRK pin with no voltage setting in order to determine whether the load device is capa- external components required. During ramp-up, the output voltage ble of operating over its specifi ed supply voltage range. This provides follows the VTRK voltage until the preset output voltage level is met. a convenient method for dynamically testing the operation of the load The product offers two modes of tracking as follows: circuit over its supply margin or range. It can also be used to verify the 1. Coincident. This mode confi gures the product to ramp its output function of supply voltage supervisors. Margin limits of the nominal voltage at the same rate as the voltage applied to the VTRK pin. output voltage ±5% are default, but the margin limits can be reconfi g- ured using the PMBus interface. VOUT Pre-Bias Startup Capability MASTER Pre-bias startup often occurs in complex digital systems when current from another power source is fed back through a dual-supply logic component, such as FPGAs or ASICs. The product family incorporates synchronous rectifi ers, but will not sink current during startup, or turn off, or whenever a fault shuts down the product in a pre-bias condi- SLAVE tion. Pre-bias protection is not offered for current sharing groups that also have voltage tracking enabled. Group Communication Bus The Group Communication Bus, GCB, is used to communicate t between products. This dedicated bus provides the communica- Illustration of Coincident Voltage Tracking. tion channel between devices for features such as sequencing, fault 2. Ratiometric. This mode confi gures the product to ramp its output spreading, and current sharing. The GCB solves the PMBus data rate voltage at a rate that is a percentage of the voltage applied to the limitation. The GCB pin on all devices in an application should be con- VTRK pin. The default setting is 50%, but a different tracking ratio nected together. A pull-up resistor is required on the common GCB in may be set by an external resistive voltage divider or through the order to guarantee the rise time as follows: PMBus interface. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 25 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Eq. 5.  = R C ≤ 1μs, Products with P2 as reference OTP: GCB GCB When TP2 as defi ned in thermal consideration section exceeds 120°C where R is the pull up resistor value and C is the bus loading. GCB GCB the product will shut down. For products with P2 as a reference for The pull-up resistor should be tied to an external supply voltage in OTP the confi gured default value in the controller circuit in position P2 range from 3.3 to 5 V, which should be present priorμ to or during is 120°C. power-up. The OTP threshold, hysteresis, and fault response of the product If exploring untested compensation or deadtime confi gurations, it is can be reconfi gured using the PMBus interface. The fault response recommended that 27 Ω series resistors are placed between the GCB can be confi gured as follows: pin of each product and the common GCB connection. This will avoid 1. Initiate a shutdown and attempt to restart an infi nite number propagation of faults between products potentially caused by hazard- of times with a preset delay period between attempts (default ous confi guration settings. When the confi gurations of the products confi guration). are settled the series resistors can be removed. 2. Initiate a shutdown and attempt to restart a preset number of The GCB is an internal bus, such that it is only connected across times with a preset delay period between attempts. the modules and not the PMBus system host. GCB addresses are assigned on a rail level, i.e. modules within the same current sharing 3. Continue operating for a given delay period, followed by shutdown group share the same GCB address. Addressing rails across the GCB if the fault still exists. is done with a 5 bit GCB ID, yielding a theoretical total of 32 rails that 4. Continue operating through the fault (this could result in perma- can be shared with a single GCB bus. nent damage to the power supply). Fault spreading 5. Initiate an immediate shutdown. The product can be confi gured to broadcast a fault event over the Optimization examples GCB bus to the other devices in the group. When a non-destructive This product is designed with a digital control circuit. The control fault occurs and the device is confi gured to shut down on a fault, the circuit uses a confi guration fi le which determines the functionality and device will shut down and broadcast the fault event over the GCB bus. performance of the product. It is possible to change the confi gura- The other devices on the GCB bus will shut down together if confi g- tion fi le to optimize certain performance characteristics. In the table ured to do so, and will attempt to re-start in their prescribed order if below is a schematic view on how to change different confi guration confi gured to do so. parameters in order to achieve an optimization towards a wanted Over Temperature Protection (OTP) performance. The products are protected from thermal overload by an internal over Increase  temperature shutdown function in the controller circuit N1, located at  No change  Decrease position P2 (see section Thermal Consideration). Some of the products that this specifi cation covers use the temperature at position P2 (TP2) Control Diode Config. Switching NLR Min. loop emulation as a reference for specifi ed OTP threshold and some use position pulse parameters frequency threshold bandwidth (DCM) P1 (TP1) as a reference for specifi ed OTP threshold. See the Over Optimized performance Temperature Protection section in the electrical specifi cation for each Maximize   Enable Disable product. effi ciency Enable Minimize Enable or Products with P1 as reference for OTP:   or ripple ampl. disable disable When TP1 as defi ned in thermal consideration section exceeds Improve load transient approximately 120 °C the product will shut down. The specifi ed OTP   Disable Disable response threshold and hysteresis are valid for worst case operation regarding Minimize   Enable Enable cooling conditions, input voltage and output voltage. The actually con- idle power loss fi gured default value in the controller circuit in position P2 is 110 °C, Note 1: The following table, graphs, and waveforms are only examples and valid for but at worst case operation the temperature is approximately 10 °C OKDX-T/50-W12-001-C. Note 2: In the following table and graphs, the worst-case scenario (load step 37.5-12.5 higher at position P1. At light load the temperature is approximately A) has been considered for load transient. the same in position P1 and P2. This means the OTP threshold and hysteresis will be lower at light load conditions when P1 is used as a reference for OTP. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 26 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series V = 0.6 V 0.95 O Efficiency vs. Output Current and Switching frequency Default confi gura- V = 1.0 V 0.95 tion: Continues O W [%] Conduction Mode, V = 1.8 V 1.22 O 95 CCM V = 3.3 V 1.88 O V = 0.6 V 0.21 O 90 DCM, Discontin- 200 V = 1.0 V 0.21 Input idling power ues Conduction O kHz P W li (no load) Mode 85 V = 1.8 V 0.21 320 O kHz (diode emulation) V = 3.3 V 0.21 O 480 80 V = 0.6 V 0.43 kHz O DCM with 640 V = 1.0 V 0.46 O 75 kHz Minimum Pulse W V = 1.8 V 0.54 O Enabled V = 3.3 V 0.67 70 O 001 02 03 40 50 [A] Default confi gura- tion: 170 mW Monitoring Efficiency vs. load current and switching frequency at T = +25 °C, V = 12 V, V = 1.0 V, C = 470 μF/10 mΩ enabled P1 I O O Default configuration except changed frequency Pulse monitor Input standby Turned off with mode: P 109 mW CTRL Load transient vs. Switching frequency power CTRL-pin Monitoring disabled [mV] Low power mode: 600 Monitoring 85 mW Universal PID, No NLR disabled 500 DLC, V = 0.6 V 300 O No NLR Default confi gura- 400 V = 1.0 V 300 Universal PID, tion O Load transient mV Default NLR di/dt = 2 A/μs peak voltage V = 1.8 V 305 300 O DLC, C = 470 μF deviation O V = 3.3 V 315 Default NLR O 200 V tr1 Universal PID, DLC and V = 0.6 V 100 O Load step Opt. NLR Optimized NLR 100 25-75-25% of V = 1.0 V 100 O DLC, confi guration mV max I O Opt. NLR V = 1.8 V 100 O 0 di/dt = 2 A/μs 200 300 400 500 600 [kHz] C = 470 μF V = 3.3 V 100 O O V = 0.6 V 100 O Default confi gu- Load transient peak voltage deviation vs. frequency. V = 1.0 V 100 ration O Step-change (12.5-37.5-12.5 A). Load transient di/dt = 2 A/μs V = 1.8 V 100 T = +25 °C, V = 12 V, V =1.0 V, C = 470 μF/10 mΩ P1 I O O O recovery time C =470 μF O V = 3.3 V 100 O t μs Power Dissipation vs. Output Current and Switching frequency tr1 Load step DLC and V = 0.6 V 50 O 25-75-25% of Optimized NLR V = 1.0 V 50 O [W] max I O confi guration V = 1.8 V 50 O di/dt = 2 A/μs 12 C = 470 μF V = 3.3 V 50 O O 10 200 kHz 8 320 kHz 6 480 kHz 4 640 kHz 2 0 0 10 020304 50 [A] Dissipated power vs. load current and switching frequency at TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 μF/10 mΩ Default configuration except changed frequency www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 27 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Output Load Transient Response, Default Configuration Output Ripple vs. Switching frequency [mV ] pk-pk 60 50 0.6 V 40 1.0 V 30 1.8 V 3.3 V 20 10 0 [kHz] 200 300 400 500 600 Output voltage response to load current step-change Top trace: output voltage (200 mV/div.). (12.5-37.5-12.5 A) at: Bottom trace: load current (10 A/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (0.1 ms/div.). Output voltage ripple V at: T = +25 °C, V = 12 V, C = 470 μF/10 mΩ, pk-pk P1 I O di/dt=2 A/μs, fsw = 320 kHz, CO = 470 μF/10 mΩ IO = 50 A resistive load. Default configuration except changed frequency. Default configuration (DLC and default NLR) Load Transient vs. Decoupling Capacitance, V = 1.0 V Output Load Transient Response, DLC and No NLR O [mV] 500 Universal PID, No NLR 400 DLC, No NLR Universal PID, 300 Default NLR DLC, 200 Default NLR Universal PID, 100 Opt. NLR DLC, Opt. NLR 0 01 235 4 [mF] Output voltage response to load current step-change Top trace: output voltage (200 mV/div.). (12.5-37.5-12.5 A) at: Bottom trace: load current (10 A/div.). Load transient peak voltage deviation vs. decoupling capacitance. TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (0.1 ms/div.). di/dt=2 A/μs, fsw = 320 kHz, CO = 470 μF/10 mΩ Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mΩ, DLC and no NLR TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/μs Load Transient vs. Decoupling Capacitance, V = 3.3 V Output Load Transient Response, DLC and Optimized NLR O [mV] 500 Universal PID, No NLR 400 DLC, No NLR Universal PID, 300 Default NLR DLC, 200 Default NLR Universal PID, Opt. NLR 100 DLC, Opt. NLR 0 03 1 2 45 [mF] Output voltage response to load current step-change Top trace: output voltage (200 mV/div.). (12.5-37.5-12.5 A) at: Bottom trace: load current (10 A/div.). Load transient peak voltage deviation vs. decoupling capacitance. TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (0.1 ms/div.). Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 μF/10 mΩ, di/dt=2 A/μs, fsw = 320 kHz, CO = 470 μF/10 mΩ TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/μs DLC and optimized NLR www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 28 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Thermal Consideration AIR FLOW General The product is designed to operate in different thermal environments and suffi cient cooling must be provided to ensure reliable operation. P1 P2 Cooling is achieved mainly by conduction, from the pins to the host board, and convection, which is dependent on the airfl ow across the product. Increased airfl ow enhances the cooling of the product. The Output Current Derating graph found in the Output section SIP Version:Temperature positions and air fl ow direction. for each model provides the available output current vs. ambient air Defi nition of reference temperature TP1 temperature and air velocity at specifi ed VI. The reference temperature is used to monitor the temperature limits The product is tested on a 254 x 254 mm, 35 μm (1 oz), test board of the product. Temperature above maximum TP1, measured at the mounted vertically in a wind tunnel with a cross-section of 608 x 203 reference point P1 is not allowed and may cause degradation or mm. The test board has 8 layers. permanent damage to the product. TP1 is also used to defi ne the temperature range for normal operating conditions. TP1 is defi ned by Proper cooling of the product can be verifi ed by measuring the tem- the design and used to guarantee safety margins, proper operation perature at positions P1 and P2. The temperature at these positions and high reliability of the product. should not exceed the max values provided in the table below. Note that the max value is the absolute maximum rating (non destruction) and that the electrical Output data is guaranteed up to TP1 +95°C. Defi nition of product operating temperature The product operating temperatures are used to monitor the tempera- ture of the product, and proper thermal conditions can be verifi ed by measuring the temperature at positions P1 and P2. The temperature at these positions (TP1, TP2) should not exceed the maximum tem- peratures in the table below. The number of measurement points may vary with different thermal design and topology. Temperatures above maximum TP1, measured at the reference point P1 are not allowed and may cause permanent damage. It should also be noted that depending on setting of the over temperature protection (OTP) and Pin layout, top view (component placement for illustration only). operating conditions, the product may shut down before the maximum allowed temperature at TP1 is reached. Pin Designation Function 1A, 1B VIN Input Voltage Position Description Max Temp. * 2A, 2B GND Power Ground P1 Reference point, L1, inductor 125°C * 3A, 3B VOUT Output Voltage P2 N1, control circuit 125°C 4A VTRK Voltage Tracking input * A guard band of 5 °C is applied to the maximum recorded component temperatures 4B PREF Pin-strap reference when calculating output current derating curves. 5A +S Positive sense 5B −S Negative sense AIR FLOW 6A SA0 PMBus address pinstrap 0 6B GCB Group Communication Bus Top view Bottom view 7A SCL PMBus Clock 7B SDA PMBus Data 8A VSET Output voltage pinstrap P1 P2 8B SYNC Synchronization I/O 9A SALERT PMBus Alert 9B CTRL Remote Control 10A PG Power Good 10B SA1 PMBus address pinstrap 1 Temperature positions and air fl ow direction. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 29 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Unused input pins Unused SDA, SCL and GCB pins should still have pull-up resistors as specifi ed. Unused VTRK or SYNC pins should be left open or connected to the PREF pin. SIP Version: Pin layout, top view (component placement for illustration only). Unused CTRL pin can be left open due to internal pull-up. Pin Designation Function VSET and SA0/SA1 pins must be used. These pins must have pin- 1A, 1B VIN Input Voltage strap resistors or strapping settings as specifi ed. 2A, 2B GND Power Ground 3A, 3B VOUT Output Voltage PWB layout considerations 4A +S Positive sense 4B −S Negative sense The pin-strap resistors, RSET, and RSA0/RSA1 should be placed as 5A VSET Output voltage pinstrap close to the product as possible to minimize loops that may pick up 5B VTRK Voltage Tracking input noise. 6A SALERT PMBus Alert 6B SDA PMBus Data Avoid current carrying planes under the pin-strap resistors and the 7A SCL PMBus Clock PMBus signals. 7B SA1 PMBus address pinstrap 1 8A SA0 PMBus address pinstrap 0 The capacitor CI (or capacitors implementing it) should be placed 8B SYNC Synchronization I/O as close to the input pins as possible. 9A PG Power Good 9B CTRL Remote Control Capacitor CO (or capacitors implementing it) should be placed close 10A GCB Group Communication Bus to the load. 10B PREF Pin-strap reference Care should be taken in the routing of the connections from the sensed output voltage to the S+ and S– terminals. These sensing connections should be routed as a differential pair, preferably between ground planes which are not carrying high currents. The routing should avoid areas of high electric or magnetic fi elds. Typical Application Circuit Standalone operation with PMBus communication. Top view of product footprint. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 30 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Typical Application Circuit (SIP version) Standalone operation with PMBus communication. Top view of product footprint. Typical Application Circuit (Parallel Operation) www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 31 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series PMBus interface The Snapshot feature enables the user to read the parameters via the PMBus interface during normal operation, although it should be This product provides a PMBus digital interface that enables the user noted that reading the 22 bytes will occupy the bus for some time. to confi gure many aspects of the device operation as well as to moni- The Snapshot enables the user to store the snapshot parameters to tor the input and output voltages, output current and device tem- 2 Flash memory in response to a pending fault as well as to read the perature. The product can be used with any standard two-wire I C or stored data from Flash memory after a fault has occurred. Automatic SMBus host device. In addition, the product is compatible with PMBus store to Flash memory following a fault is triggered when any fault version 1.1 and includes an SALERT line to help mitigate bandwidth threshold level is exceeded, provided that the specifi c fault response limitations related to continuous fault monitoring. The product sup- is to shut down. Writing to Flash memory is not allowed if the device ports 100 kHz bus clock frequency only. The PMBus signals, SCL, SDA is confi gured to restart following the specifi c fault condition. It should and SALERT require passive pull-up resistors as stated in the SMBus also be noted that the device supply voltage must be maintained Specifi cation. Pull-up resistors are required to guarantee the rise time during the time the device is writing data to Flash memory; a process as follows: that requires between 700-1400 μs depending on whether the data Eq. 6.  = R C ≤ 1μs, p p is set up for a block write. Undesirable results may be observed if the where R is the pull-up resistor value and C is the bus loading, the input voltage of the product drops below 3.0 V during this process. p p maximum allowed bus load is 400 pF. The pull-up resistor should be Non-Volatile Memory (NVM) tied to an external supply voltage in range from 2.7 to 5.5 V, which The product incorporates two Non-Volatile Memory areas for storage of should be present prior to or during power-up. If the proper power the supported PMBus commands; the Default NVM and the User NVM. supply is not available, voltage dividers may be applied. Note that in this case, the resistance in the equation above corresponds to parallel The Default NVM is pre-loaded with Murata factory default connection of the resistors forming the voltage divider. values. The Default NVM is write-protected and can be used to restore the Murata factory default values through the command Monitoring via PMBus RESTORE_DEFAULT_ALL. It is possible to monitor a wide variety of parameters through the The User NVM is pre-loaded with Murata factory default values. The PMBus interface. Fault conditions can be monitored using the SALERT User NVM is writable and open for customization. The values in NVM pin, which will be asserted when any number of pre-confi gured fault are loaded into operational RAM during initialization according to sec- or warning conditions occurs. It is also possible to continuously moni- tion “Initialization Procedure”, where after commands can be changed tor one or more of the power conversion parameters including but not through the PMBus Interface. The STORE_USER_ALL command will limited to the following: store the changed parameters to the User NVM.  Input voltage (READ_VIN)  Output voltage (READ_VOUT) INITIALIZATION User NVM  Output current (READ_IOUT) Factory default STORE_USER_ALL  Internal junction temperature (READ_TEMPERATURE_1) Customizable  Switching frequency (READ_FREQUENCY) RESTORE USER ALL  Duty cycle (READ_DUTY_CYCLE) INITIALIZATION Default NVM In the default confi guration monitoring is enabled also when the RAM Factory default output voltage is disabled. This can be changed in order to reduce RESTORE_DEFAULT_ALL Write-protected standby power consumption. WRITE Snap shot parameter capture PMBus interface This product offers a special feature that enables the user to capture READ parametric data during normal operation or following a fault. The fol- lowing parameters are stored: Software tools for design and production  Input voltage Murata provides software tools for confi guration and monitoring of  Output voltage this product via the PMBus interface. For more information please  Output current contact your local Murata sales representative.  Internal junction temperature PMBus addressing  Switching frequency The PMBus address should be confi gured with resistors connected  Duty cycle between the SA0/SA1 pins and the PREF pin, as shown in the  Status registers www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 32 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series fi gure below. Recommended resistor values for hard-wiring PMBus Reserved Addresses addresses are shown in the table. 1% tolerance resistors are required. Address 4Bh is allocated for production needs and cannot be used. Addresses listed in the table below are reserved or assigned according to the SMBus specifi cation and may not be usable. Refer to SA0 SA1 the SMBus specifi cation for further information. Address R R SA1 SA0 Comment (decimal) 0 General Call Address / START byte PREF 1 CBUS address 2 Address reserved for different bus format 3-7 Reserved for future use 8 SMBus Host Schematic of connection of address resistor. 9-11 Assigned for Smart Battery 12 SMBus Alert Response Address Index R [kΩ] Index R [kΩ] SA SA 40 Reserved for ACCESS.bus host 0 10 13 34.8 44-45 Reserved by previous versions of the SMBus specifi cation 1 11 14 38.3 55 Reserved for ACCESS.bus default address 2 12.1 15 42.2 64-68 Reserved by previous versions of the SMBus specifi cation 3 13.3 16 46.4 72-75 Unrestricted addresses 4 14.7 17 51.1 97 SMBus Device Default Address 5 16.2 18 56.2 120-123 10-bit slave addressing 6 17.8 19 61.9 124-127 Reserved for future use 7 19.6 20 68.1 8 21.5 21 75 2 I C/SMBus – Timing 9 23.7 22 82.5 10 26.1 23 90.9 11 28.7 24 100 12 31.6 The PMBus address follows the equation below: Eq. 7. PMBus Address (decimal) = 25 x (SA1 index) + (SA0 index) The user can theoretically confi gure up to 625 unique PMBus addresses, however the PMBus address range is inherently limited to 128. Therefore, the user should use index values 0 - 4 on the SA1 pin and the full range of index values on the SA0 pin, which will provide Setup and hold times timing diagram 125 device address combinations. The user shall also be aware of further limitations of the address space as stated in the SMBus The setup time, tset, is the time data, SDA, must be stable before the Specifi cation. lock signal, SCL. The hold time thold, is the time rising edge of the c data, SDA, must be stable after the rising edge of the clock signal, Note that address 0x4B is allocated for production needs and SCL. If these times are violated incorrect data may be captured or cannot be used. meta-stability may occur and the bus communication may fail. When Optional PMBus Addressing confi guring the product, all standard SMBus protocols must be fol- lowed, including clock stretching. Refer to the SMBus specifi cation, for Alternatively the PMBus address can be defi ned by connecting the SMBus electrical and timing requirements. SA0/SA1 pins according to the table below. SA1 = open for products with no SA1 pin. This product does not support the BUSY fl ag in the status commands to indicate product being too busy for SMBus response. Instead a bus- SA0 free time delay according to this specifi cation must occur between low open high every SMBus transmission (between every stop & start condition). In low 20h 21h 22h case of storing the RAM content into the internal non-volatile memory SA1 open 23h 24h 25h (commands STORE_USER_ALL and STORE_DEFAULT_ALL) an addi- high 26h 27h Reserved tional delay of 100 ms has to be inserted. A 100 ms delay should be Low = Shorted to PREF Open = High impedance inserted after a restore from internal non-volatile memory (commands High = Logic high, GND as reference, RESTORE_DEFAULT_ALL and RESTORE_USER_ALL). Logic High defi nitions see Electrical Specifi cation www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 33 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series PMBus Commands Designation Cmd Impl The products are PMBus compliant. The following table lists the TON_RISE 61h Yes TOFF_DELAY 64h Yes implemented PMBus read commands. For more detailed information TOFF_FALL 65h Yes see PMBus Power System Management Protocol Specifi cation; Part I TON_MAX_FAULT_LIMIT 62h No – General Requirements, Transport and Electrical Interface and PMBus Status Commands (Read Only) Power System Management Protocol; Part II – Command Language. CLEAR_FAULTS 03h Yes Designation Cmd Impl STATUS_BYTE 78h Yes Standard PMBus Commands STATUS_WORD 79h Yes Control Commands STATUS_VOUT 7Ah Yes PAGE 00h No STATUS_IOUT 7Bh Yes OPERATION 01h Yes STATUS_INPUT 7Ch Yes ON_OFF_CONFIG 02h Yes STATUS_TEMPERATURE 7Dh Yes WRITE_PROTECT 10h No STATUS_CML 7Eh Yes Output Commands STATUS_MFR_SPECIFIC 80h Yes VOUT_MODE (Read Only) 20h Yes Monitor Commands (Read Only VOUT_COMMAND 21h Yes READ_VIN 88h Yes VOUT_TRIM 22h Yes READ_VOUT 8Bh Yes VOUT_CAL_OFFSET 23h Yes READ_IOUT 8Ch Yes VOUT_MAX 24h Yes READ_TEMPERATURE_1 8Dh Yes VOUT_MARGIN_HIGH 25h Yes READ_TEMPERATURE_2 8Eh No VOUT_MARGIN_LOW 26h Yes READ_FAN_SPEED_1 90h No VOUT_TRANSITION_RATE 27h Yes READ_DUTY_CYCLE 94h Yes VOUT_DROOP 28h Yes READ_FREQUENCY 95h Yes MAX_DUTY 32h Yes Group Commands FREQUENCY_SWITCH 33h Yes INTERLEAVE 37h Yes VIN_ON 35h No PHASE_CONTROL F0h Yes VIN_OFF 36h No Identifi cation Commands IOUT_CAL_GAIN 38h Yes PMBUS_REVISION 98h Yes IOUT_CAL_OFFSET 39h Yes MFR_ID 99h Yes VOUT_SCALE_LOOP 29h No MFR_MODEL 9Ah Yes VOUT_SCALE_MONITOR 2Ah No MFR_REVISION 9Bh Yes COEFFICIENTS 30h No MFR_LOCATION 9Ch Yes Fault Limit Commands MFR_DATE 9Dh Yes POWER_GOOD_ON 5Eh Yes MFR_SERIAL 9Eh Yes POWER_GOOD_OFF 5Fh No Supervisory Commands VOUT_OV_FAULT_LIMIT 40h Yes STORE_DEFAULT_ALL 11h Yes VOUT_OV_WARN_LIMIT 42h No RESTORE_DEFAULT_ALL 12h Yes VOUT_UV_WARN_LIMIT 43h No STORE_USER_ALL 15h Yes VOUT_UV_FAULT_LIMIT 44h Yes RESTORE_USER_ALL 16h Yes IOUT_OC_FAULT_LIMIT 46h Yes Product Specifi c Commands IOUT_OC_WARN_LIMIT 4Ah No Output Commands IOUT_UC_FAULT_LIMIT 4Bh Yes XTEMP_SCALE D9h No OT_FAULT_LIMIT 4Fh Yes XTEMP_OFFSET DAh No OT_WARN_LIMIT 51h Yes Time Setting Commands UT_WARN_LIMIT 52h Yes POWER_GOOD_DELAY D4h Yes UT_FAULT_LIMIT 53h Yes Fault limit Commands VIN_OV_FAULT_LIMIT 55h Yes IOUT_AVG_OC_FAULT_LIMIT E7h Yes VIN_OV_WARN_LIMIT 57h Yes IOUT_AVG_UC_FAULT_LIMIT E8h Yes VIN_UV_WARN_LIMIT 58h Yes Fault Response Commands VIN_UV_FAULT_LIMIT 59h Yes MFR_IOUT_OC_FAULT_RESPONSE E5h Yes Fault Response Commands MFR_IOUT_UC_FAULT_RESPONSE E6h Yes VOUT_OV_FAULT_RESPONSE 41h Yes OVUV_CONFIG D8h Yes VOUT_UV_FAULT_RESPONSE 45h Yes Confi guration and Control Commands OT_FAULT_RESPONSE 50h Yes MFR_CONFIG D0h Yes UT_FAULT_RESPONSE 54h Yes USER_CONFIG D1h Yes VIN_OV_FAULT_RESPONSE 56h Yes MISC_CONFIG E9h Yes VIN_UV_FAULT_RESPONSE 5Ah Yes TRACK_CONFIG E1h Yes IOUT_OC_FAULT_RESPONSE 47h No PID_TAPS D5h Yes * IOUT_UC_FAULT_RESPONSE 4Ch No PID_TAPS_CALC F2h Yes Time setting Commands INDUCTOR D6h Yes TON_DELAY 60h Yes NLR_CONFIG D7h Yes www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 34 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Designation Cmd Impl TEMPCO_CONFIG DCh Yes * IOUT_OMEGA_OFFSET BEh Yes ** AUTO_COMP_CONTROL BDh Yes ** AUTO_COMP_CONFIG BCh Yes DEADTIME DDh Yes DEADTIME_CONFIG DEh Yes DEADTIME_MAX BFh Yes SNAPSHOT EAh Yes SNAPSHOT_CONTROL F3h Yes DEVICE_ID E4h Yes USER_DATA_00 B0h Yes Group Commands SEQUENCE E0h Yes GCB_CONFIG D3h Yes GCB_GROUP E2h Yes ISHARE_CONFIG D2h Yes PHASE_CONTROL F0h Yes Supervisory Commands PRIVATE_PASSWORD FBh Yes PUBLIC_PASSWORD FCh Yes UNPROTECT FDh Yes SECURITY_LEVEL FAh Yes Notes: Cmd is short for Command. Impl is short for Implemented. * These commands are available in products without DLC. ** These commands are available in products with DLC. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 35 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-THROUGH-HOLE MOUNT All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 36 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-SURFACE MOUNT All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 37 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series MECHANICAL SPECIFICATIONS-SIP VERSION All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle, unless explicitly described and dimensioned in this drawing. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 38 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Soldering Information - Surface Mounting and Hole Mount Lead-free (Pb-free) solder processes through Pin in Paste Assembly For Pb-free solder processes, a pin temperature (TPIN) in excess of The product is intended for forced convection or vapor phase refl ow the solder melting temperature (TL, 217 to 221°C for SnAgCu solder soldering in SnPb or Pb-free processes. alloys) for more than 60 seconds and a peak temperature of 245°C on all solder joints is recommended to ensure a reliable solder joint. The refl ow profi le should be optimised to avoid excessive heating of the product. It is recommended to have a suffi ciently extended Maximum Product Temperature Requirements preheat time to ensure an even temperature across the host PWB and Top of the product PWB near pin 10B is chosen as reference location it is also recommended to minimize the time in refl ow. for the maximum (peak) allowed product temperature (TPRODUCT) since this will likely be the warmest part of the product during the refl ow A no-clean fl ux is recommended to avoid entrapment of cleaning process. fl uids in cavities inside the product or between the product and the host board, since cleaning residues may affect long time reliability SnPb solder processes and isolation voltage. For SnPb solder processes, the product is qualifi ed for MSL 1 accord- General reflow process specifications SnPb eutectic Pb-free ing to IPC/JEDEC standard J STD 020C. Average ramp-up (T ) 3°C/s max 3°C/s max PRODUCT Typical solder melting (liquidus) During refl ow TPRODUCT must not exceed 225 °C at any time. T 183°C 221°C L temperature Minimum refl ow time above T 60 s 60 s L Pb-free solder processes Minimum pin temperature T PIN 210°C 235°C For Pb-free solder processes, the product is qualifi ed for MSL 3 Peak product temperature T 225°C 260°C PRODUCT Average ramp-down (T ) 6°C/s max 6°C/s max according to IPC/JEDEC standard J-STD-020C. PRODUCT Maximum time 25°C to peak 8 minutes 6 minutes During refl ow TPRODUCT must not exceed 260 °C at any time. Dry Pack Information Temperature Products intended for Pb-free refl ow soldering processes are T maximum PRODUCT T minimum delivered in standard moisture barrier bags according to IPC/JEDEC Pin PIN profile standard J STD 033 (Handling, packing, shipping and use of moisture/ T L refl ow sensitivity surface mount devices). Product profile Using products in high temperature Pb-free soldering processes Time in requires dry pack storage and handling. In case the products have reflow Time in preheat been stored in an uncontrolled environment and no longer can be / soak zone considered dry, the modules must be baked according to J STD 033. Time 25°C to peak Time Thermocoupler Attachment Minimum Pin Temperature Recommendations Pin 10B for measurement of maximum Product temperature T PRODUCT Pin number 2B is chosen as reference location for the minimum pin temperature recommendation since this will likely be the coolest solder joint during the refl ow process. SnPb solder processes For SnPb solder processes, a pin temperature (TPIN) in excess of the solder melting temperature, (TL, 183°C for Sn63Pb37) for more than 60 seconds and a peak temperature of 220°C is recommended to ensure a reliable solder joint. For dry packed products only: depending on the type of solder paste and fl ux system used on the host board, up to a recommended maximum temperature of 245°C could be used, if the products are Pin 2B for measurement of minimum Pin (solder joint) kept in a controlled environment (dry pack handling and storage) prior temperature TPIN to assembly. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 39 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Soldering Information - Hole Mounting The hole mounted product is intended for plated through hole mount- ing by wave or manual soldering. The pin temperature is specifi ed to maximum to 270°C for maximum 10 seconds. A maximum preheat rate of 4°C/s and maximum preheat tempera- ture of 150°C is suggested. When soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. A no-clean fl ux is recommended to avoid entrapment of cleaning fl uids in cavities inside the product or between the product and the host board. The cleaning residues may affect long time reliability and isolation voltage. Delivery Package Information The products are delivered in antistatic carrier tape (EIA 481 standard). Carrier Tape Specifications Material Antistatic PS 7 Surface resistance <10 Ohm/square Bakeability The tape is not bakable Tape width, W 56 mm [2.20 inch] Pocket pitch, P 32 mm [1.26 inch] 1 Pocket depth, K 13 mm [0.51 inch] 0 Reel diameter 381 mm [15 inch] Reel capacity 130 products /reel Reel weight 1.8 kg/full reel www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 40 of 41 OKDx-T/50-W12-C 50A Digital PoL DC-DC Converter Series Soldering Information - Hole Mounting (SIP version) The product is intended for plated through hole mounting by wave or manual soldering. The pin temperature is specifi ed to maximum to 270°C for maximum 10 seconds. A maximum preheat rate of 4°C/s and maximum preheat tempera- ture of 150°C is suggested. When soldering by hand, care should be taken to avoid direct contact between the hot soldering iron tip and the pins for more than a few seconds in order to prevent overheating. A no-clean fl ux is recommended to avoid entrapment of cleaning fl uids in cavities inside the product or between the product and the host board. The cleaning residues may affect long time reliability and isolation voltage. Delivery Package Information (SIP version) The products are delivered in antistatic trays. Tray Specifications Material Antistatic Polyethylene foam 5 11 Surface resistance 10 < Ohms/square <10 Bakability The trays are not bakeable Tray thickness 15 mm [0.709 inch] Box capacity 100 products, 2 full trays/box) Tray weight 35 g empty tray, 549 g full tray This product is subject to the following operating requirements Murata Power Solutions, Inc. and the Life and Safety Critical Application Sales Policy: 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 U.S.A. Refer to: http://www.murata-ps.com/requirements/ ISO 9001 and 14001 REGISTERED Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. © 2017 Murata Power Solutions, Inc. www.murata-ps.com/support MDC_OKDx-T/50-W12-C.A06 Page 41 of 41