ADS-944 14-Bit, 5MHz Sampling A/D Converters PRODUCT OVERVIEW The low-cost ADS-944 is a high-performance, logic, three-state outputs, and errorcorrection 14-bit, 5MHz sampling A/D converter. This device circuitry. Digital input and output levels are TTL. accurately samples fullscale input signals up to Requiring ±15V, +5V and –5.2V supplies, the Nyquist frequencies with no missing codes. The ADS-944 typically dissipates 2.95 Watts. The unit dynamic performance of the ADS-944 has been opti- is offered with a bipolar input range of ±1.25V. mized to achieve a THD of –77dB and a SNR of 76dB. Models are available in commercial (0 to +70°C), Packaged in a small, 32-pin TDIP, the function- industrial (–40 to +100°C), or HI-REL (–55 to ally complete ADS-944 contains a fast-settling +125°C) operating temperature ranges. Typical sample-hold amplifi er, a subranging (two-pass) A/D applications include radar signal analysis, medical/ converter, an internal reference, timing and control graphic imaging, and FFT spectrum analysis. INPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION 1 +5V ANALOG SUPPLY 32 START CONVERT FEATURES 2 –5.2V DIGITAL SUPPLY 31 BIT 1 (MSB) 3 ANALOG INPUT 30 BIT 1 (MSB) „ 14-bit resolution 4 ANALOG GROUND 29 BIT 2 „ 5MHz minimum sampling rate 5 OFFSET ADJUST 28 BIT 3 6 ANALOG GROUND 27 BIT 4 „ No missing codes over full HI-REL temperature 7 GAIN ADJUST 26 BIT 5 range 8 COMP. BITS 25 BIT 6 „ Edge-triggered, no pipeline delay 9 OUTPUT ENABLE 24 BIT 7 10 +5V DIGITAL SUPPLY 23 BIT 8 „ Low power, 2.95 Watts 11 ANALOG GROUND 22 BIT 9 „ Small, 32-pin, ceramic TDIP package 12 +15V SUPPLY 21 BIT 10 13 –15V SUPPLY 20 BIT 11 „ SMT package available 14 –5.2V ANALOG SUPPLY 19 BIT 12 „ Excellent dynamic performance 15 DIGITAL GROUND 18 BIT 13 16 EOC 17 BIT 14 (LSB) „ MIL-STD-883 screening or DESC SMD available BLOCK DIAGRAM 31 BIT 1 (MSB) BUFFER ANALOG INPUT 3 – 30 BIT 1 (MSB) S/H FLASH 29 BIT 2 + ADC 28 BIT 3 1 27 BIT 4 26 BIT 5 GAIN REF 25 BIT 6 GAIN ADJUST 7 CIRCUIT DAC 24 BIT 7 Σ 23 BIT 8 22 BIT 9 21 BIT 10 FLASH 20 BIT 11 ADC 19 BIT 12 OFFSET 2 AMP OFFSET ADJUST 5 CIRCUIT 18 BIT 13 17 BIT 14 (LSB) START CONVERT 32 TIMING AND 9 OUTPUT ENABLE CONTROL LOGIC EOC 16 1 2 4, 6, 11 10 12 14 15 8 +5V –5.2V ANALOG +5V +15V –5.2V DIGITAL COMP. ANALOG DIGITAL GROUND DIGITAL SUPPLY ANALOG GROUND BITS SUPPLY SUPPLY SUPPLY SUPPLY Figure 1. ADS-944 Functional Block Diagram DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 1 of 9 DIGITAL CORRECTION LOGIC 3-STATE OUTPUT REGISTER ADS-944 14-Bit, 5MHz Sampling A/D Converters ABSOLUTE MAXIMUM RATINGS PHYSICAL/ENVIRONMENTAL PARAMETERS LIMITS UNITS PARAMETERS MIN. TYP. MAX. UNITS +15V Supply (Pins 12) 0 to +16 Volts Operating Temp. Range, Case –15V Supply (Pin 13) 0 to –16 Volts ADS-944MC, MC-C 0 — +70 °C +5V Supply (Pins 1, 10) 0 to +6 Volts ADS-944ME, ME-C –40 — +100 °C –5V Supply (Pin 2, 14) 0 to –6 Volts ADS-944MM, MM-C –55 — +125 °C Digital Input (Pin 8, 9, 32) –0.3 to +VDD +0.3 Volts ADS-944/883, 883-C –55 — +125 °C Analog Input (Pin 3) –5 to +5 Volts Thermal Impedance Lead Temperature (10 seconds) +300 °C θjc — 7 — °C/Watt θca — 21 — °C/Watt Storage Temperature Range –65 — +150 °C Package Type 32-pin, metal-sealed, ceramic TDIP or SMT Weight 0.46 ounces (13 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±15V, +VDD = +5V,VDD = –5.2V, 5MHz sampling rate, and a minimum 3 minute warmup ➀ unless otherwise specifi ed.) +25°C 0 TO +70°C –55 TO +125°C ANALOG INPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Input Voltage Range — ±1.25 — — ±1.25 — — ±1.25 — Volts Input Resistance 500 550 — 500 550 — 500 550 — Ω Input Capacitance — 6 15 — 6 15 — 6 15 pF DIGITAL INPUT Logic Levels Logic "1" +2.0 — — +2.0 — — +2.0 — — Volts Logic "0" — — +0.8 — — +0.8 — — +0.8 Volts Logic Loading "1" — — +20 — — +20 — — +20 μA — — –20 — — –20 — — –20 μA Logic Loading "0" d Start Convert Positive Pulse Width ➂ 40 80 — 40 80 — 40 80 — ns STATIC PERFORMANCE Resolution — 14 — — 14 — — 14 — Bits Integral Nonlinearity (fi n = 10kHz) — ±0.75 — — ±0.75 — — ±1.0 — LSB Differential Nonlinearity (fi n = 10kHz) –0.95 ±0.5 +1.2 –0.95 ±0.5 +1.2 –0.95 ±0.5 +1.5 LSB Full Scale Absolute Accuracy — ±0.15 ±0.4 — ±0.15 ±0.4 — ±0.4 ±1.1 %FSR Bipolar Zero Error (Tech Note 2) — ±0.1 ±0.3 — ±0.1 ±0.3 — ±0.3 ±0.9 %FSR Bipolar Offset Error (Tech Note 2) — ±0.2 ±0.4 — ±0.2 ±0.4 — ±0.3 ±1.2 %FSR Gain Error (Tech Note 2) — ±0.2 ±0.4 — ±0.2 ±0.4 — ±0.4 ±1.8 % No Missing Codes (fi n = 10kHz) 14 — — 14 — — 14 — — Bits DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 100kHz — –85 –77 — –85 –75 — –81 –71 dB 100kHz to 1MHz — –78 –71 — –78 –70 — –75 –67 dB 1MHz to 2.5MHz — –75 –70 — –75 –68 — –71 –61 dB Total Harmonic Distortion (–0.5dB) dc to 100kHz — –82 –76 — –82 –74 — –78 –70 dB 100kHz to 1MHz — –77 –70 — –77 –70 — –73 –65 dB 1MHz to 2.5MHz — –73 –68 — –73 –65 — –70 –60 dB Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 100kHz 73 76 — 73 76 — 71 75 — dB 100kHz to 1MHz 73 76 — 73 76 — 71 75 — dB 1MHz to 2.5MHz 73 75 — 73 75 — 71 75 — dB Signal-to-Noise Ratio f (& distortion, –0.5dB) dc to 100kHz 71 75 — 71 75 — 68 73 — dB 100kHz to 1MHz 70 73 — 69 73 — 65 71 — dB 1MHz to 2.5MHz 68 71 — 66 71 — 62 69 — dB Noise — 135 — — 135 — — 135 — μVrms Two-Tone Intermodulation Distortion (fi n = 2.45MHz, 1.975MHz, fs = 5MHz, –0.5dB) — –82 — — –82 — — –82 — dB Input Bandwidth (–3dB) Small Signal (–20dB input) — 20 — — 20 — — 20 — MHz Large Signal (–0.5dB input) — 13 — — 13 — — 13 — MHz Feedthrough Rejection (fi n = 2.5MHz) — 90 — — 90 — — 90 dB Slew Rate — ±110 — — ±110 — — ±110 — V/μs Aperture Delay Time — +10 — — +10 — — +10 — ns Aperture Uncertainty — 3 — — 3 — — 3 — ps rms S/H Acquisition Time ( to ±0.003%FSR, 2.5V step) — 85 90 — 85 90 — 85 90 ns Overvoltage Recovery Time ➄ — 200 — — 200 — — 200 — ns A/D Conversion Rate 5 — — 5 — — 5 — — MHz DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 2 of 9 ADS-944 14-Bit, 5MHz Sampling A/D Converters +25°C 0 TO +70°C –55 TO +125°C DIGITAL OUTPUTS MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Logic Levels Logic "1" +2.4 — — +2.4 — — +2.4 — — Volts Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts Logic Loading "1" — — –4 — — –4 — — –4 mA Logic Loading "0" — — +4 — — +4 — — +4 mA Delay, Edge of ENABLE to Output Data Valid/Invalid — — 10 — — 10 — — 10 ns Output Coding Offset Binary, Complementary Offset Binary, Two's Complement POWER REQUIREMENTS Power Supply Ranges➅ +15V Supply +14.25 +15.0 +15.75 +14.25 +15.0 +15.75 +14.25 +15.0 +15.75 Volts –15V Supply –14.25 –15.0 –15.75 –14.25 –15.0 –15.75 –14.25 –15.0 –15.75 Volts +5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 Volts –5V Supply –4.95 –5.2 –5.45 –4.95 –5.2 –5.45 –5.1 –5.2 –5.45 Volts Power Supply Currents ➆ +15V Supply — +36 +45 — +36 +45 — +36 +45 mA –15V Supply — –17 –35 — –17 –35 — –17 –35 mA +5V Supply — +173 +200 — +173 +200 — +173 +200 mA –5.2V Supply — –167 –175 — –167 –175 — –167 –175 mA Power Dissipation — 2.5 3.1 — 2.5 3.1 — 2.5 3.1 Watts Power Supply Rejection — — ±0.05 — — ±0.05 — — ±0.05 %FSR/%V Footnotes: ➀ All power supplies must be on before applying a start convert pulse. All supplies ➄ This is the time required before the A/D output data is valid after the analog input and the clock (START CONVERT) must be present during warmup periods. The is back within the specifi ed range. device must be continuously converting during this time. ➅ The minimum supply voltages of +4.9V and –5.1V for ±VDD are required for ➁ When COMP. BITS (pin 8) is low, logic loading "0" will be –350μA for this pin. –55°C operations only. The minimum limits are +4.75V and –4.95V when operating at +125°C. ➂ An 80ns wide start convert pulse is used for all production testing. The start convert pulse should be between 40 – 80ns or 130 – 160ns to ensure proper ➆ Typical +5V and –5.2V current drain breakdowns are as follows: operations. The latter range could be used for those applications requiring less +5VAnalog = +85mA –5.2VAnalog = –114mA than a 5MHz sampling rate. +5VDigital = +70mA –5.2VDigital = –53mA ➃ Effective bits is equal to: +5VTotal = +155mA –5.2VTotal = –167mA Full Scale Amplitude (SNR + Distortion) – 1.76 + 20 log Actual Input Amplitude 6.02 TECHNICAL NOTES 1. Obtaining fully specifi ed performance from the ADS-944 requires careful driven with digital logic for those who want dynamic control of its function. attention to pc-card layout and power supply decoupling. The device's ana- There is an internal pull-up resistor on this pin, allowing pin 8 to be either log and digital ground systems are not connected to each other internally. connected to +5V or left open when a logic "1" is needed. For optimal performance, tie all ground pins (4, 6, 11, and 15) directly to a 4. To enable the three-state outputs, apply a logic "0" (low) to OUTPUT ENABLE large analog ground plane beneath the package. Bypass all power supplies (pin 9). To disable, apply a logic "1" (high) to pin 9. to ground with 4.7μF tantalum capacitors in parallel with 0.1μF ceramic capacitors. It is very important that the bypass capacitors be located 5. Applying a start convert pulse while a conversion is in progress (EOC = as close to the unit as possible. Inductors or ferrite beads can also be logic "1") initiates a new and inaccurate conversion cycle. Data for the used to improve the power supply fi ltering. Refer to Figure 4, the ADS-944 interrupted and subsequent conversions will be invalid. Evaluation Board Schematic, for more details. 6. A passive bandpass fi lter is used at the input of the A/D for all production 2. The ADS-944 achieves its specifi ed accuracies without the need for exter- testing. nal calibration. If required, the device's small initial offset and gain errors 7. Though the ADS-944's digital outputs are capable of driving multiple LSTTL can be reduced to zero using the adjustment circuitry shown in Figure 2. or HCT loads, we recommend the output bits and the EOC line each drive When using this circuitry, or any similar offset and gain-calibration hard- only a single gate. These gates should be located as close to the unit as ware, make adjustments following warmup. To avoid interaction, always possible. If they can not, 33Ω resistors placed in series with each output adjust offset before gain. can aid in isolating pc run inductances. The ADS-944 digital outputs should 3. Pin 8 (COMP. BITS) selects the ADS-944's digital output coding. When a not be connected directly to noisy digital busses. logic "1" is applied to pin 8, the output coding is complementary offset 8. Do not enable/disable or complement the output bits during the conversion binary. When pin 8 has a logic "0" applied, the output coding becomes process (from the falling edge of START CONVERT to the falling edge of EOC). offset binary. The MSB output (pin 31) may be used under these conditions to achieve two's complement coding. Pin 8 is TTLcompatible and can be DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 3 of 9 ADS-944 14-Bit, 5MHz Sampling A/D Converters CALIBRATION PROCEDURE (Refer to Figure 2 and Table 1) Zero/Offset Adjust Procedure Note: Connect pin 5 to ANALOG GROUND (pin 6) for operation without 1. Apply a train of pulses to the START CONVERT input (pin 32) so the con- zero/offset adjustment. Connect pin 7 to ANALOG GROUND (pin 6) for verter is continuously converting. operation without gain adjustment. 2. Apply +76.3μV to the ANALOG INPUT (pin 3). Any offset and/or gain calibration procedures should not be implemented 3. Adjust the offset potentiometer until the output bits are 10 0000 0000 0000 until devices are fully warmed up. To avoid interaction, offset must be and the LSB fl ickers between 0 and 1 with pin 8 tied low (offset binary) or adjusted before gain. The ranges of adjustment for the circuit in Figure 2 between 01 1111 1111 1111 and 01 1111 1111 1110 with pin 8 tied high are guaranteed to compensate for the ADS-944's initial accuracy errors and (complementary offset binary). may not be able to compensate for additional system errors. 4. Two's complement coding requires using BIT 1 (MSB) (pin 31). With pin 8 A/D converters are calibrated by positioning their digital outputs exactly tied low, adjust the trimpot until the code fl ickers between 00 0000 0000 on the transition point between two adjacent digital output codes. This can 0000 and 00 0000 0000 0001. be accomplished by connecting LED's to the digital outputs and adjusting until certain LED's "fl icker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs Gain Adjust Procedure change from one code to the next. 1. Apply +1.249771V to the ANALOG INPUT (pin 3). For the ADS-944, offset adjusting is normally accomplished at the point 2. Adjust the gain potentiometer until all output bits are 1's and the LSB fl ick- where the MSB is a 1 and all other output bits are 0's and the LSB just ers between 1 and 0 with pin 8 tied low (offset binary) or until all bits are changes from a 0 to a 1. This digital output transition ideally occurs when 0's and the LSB fl ickers between 1 and 0 with pin 8 tied high (complemen- the applied analog input is +½ LSB (+76.3μV). tary offset binary). Gain adjusting is accomplished when all bits are 1's and the LSB just 3. Two's complement coding requires using pin 31. With pin 8 tied low, adjust changes from a 1 to a 0. This transition ideally occurs when the analog the gain trimpot until the output code fl ickers equally between 01 1111 input is at +full scale minus 1½ LSB's (+1.249771) . 1111 1110 and 01 1111 1111 1111. Note: Due to inherent system noise, the averaging of several conver- 4. To confi rm proper operation of the device, vary the applied input voltage to sions may be needed to accurately adjust both offset and gain to 1LSB obtain the output coding listed in Table 1. of accuracy. 31 BIT 1 (MSB) DIGITAL 30 BIT 1 (MSB) +5V 10 SUPPLY 29 BIT 2 4.7μF 0.1μF 28 BIT 3 15 27 BIT 4 26 BIT 5 4.7μF 0.1μF DIGITAL –5.2V 2 25 BIT 6 SUPPLY 24 BIT 7 23 BIT 8 ANALOG +5V 1 SUPPLY 22 BIT 9 4.7μF 0.1μF 21 BIT 10 4, 6 20 BIT 11 19 BIT 12 4.7μF 0.1μF ANALOG 14 –5.2V 18 BIT 13 SUPPLY ADS-944 17 BIT 14 (LSB) 7 OVERFLOW +15V 12 16 EOC 4.7μF 9 OUTPUT ENABLE 0.1μF 11 3 ANALOG INPUT 4.7μF START CONVERT 32 –15V 13 COMP. BITS 2 +15V +15V OFFSET GAIN 20kΩ 5 7 ADJUST ADJUST 20kΩ 0.1μF 0.1μF –15V –15V Figure 2. ADS-944 Connection Diagram DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 4 of 9 ++ ++ ++ ADS-944 14-Bit, 5MHz Sampling A/D Converters OUTPUT CODING INPUT RANGE BIPOLAR MSB LSB MSB LSB MSB LSB ±1.25V SCALE 11 1111 1111 1111 00 0000 0000 0000 01 1111 1111 1111 +1.249847 +FS –1 LSB 11 1000 0000 0000 00 1111 1111 1111 01 1000 0000 0000 +0.937500 +3/4 FS 11 0000 0000 0000 00 1111 1111 1111 01 0000 0000 0000 +0.625000 +1/2FS 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000 0.000000 0 01 0000 0000 0000 10 1111 1111 1111 11 0000 0000 0000 –0.625000 –1/2FS 00 1000 0000 0000 11 0111 1111 1111 10 1000 0000 0000 –0.937500 –3/4FS 00 0000 0000 0001 11 1111 1111 1110 10 0000 0000 0001 –1.249847 –FS +1 LSB 00 0000 0000 0000 11 1111 1111 1111 10 0000 0000 0000 –1.250000 –FS OFFSET BINARY COMP. OFF. BIN. TWO'S COMP. Table 1. Output Coding TIMING THERMAL REQUIREMENTS The ADS-944 is an edge-triggered device. A conversion is initiated by the All DATEL sampling A/D converters are fully characterized and speci- rising edge of the start convert pulse and no additional external timing sig- fi ed over operating temperature (case) ranges of 0 to +70°C and –55 nals are required. The device does not employ "pipeline" delays to increase to +125°C. All room-temperature (TA = +25°C) production testing is its throughput rate. It does not require multiple start convert pulses to bring performed without the use of heat sinks or forced-air cooling. Thermal valid digital data to its output pins. impedance fi gures for each device are listed in their respective specifi ca- tion tables. Approximately 10ns after the rising edge of the start convert signal, the ADS-944's internal sample-hold amplifi er is driven into the hold mode These devices do not normally require heat sinks, however, standard pre- by the internal S/H control line. After a 35ns delay to allow for S/H output cautionary design and layout procedures should be used to ensure devices transient settling, the conversion process begins, and the EOC line (pin 16) do not overheat. The ground and power planes beneath the package, as is driven high. The complete A/D conversion requires approximately 150ns. well as all pcb signal runs to and from the device, should be as heavy as The falling of EOC signals that the conversion is now complete and digital possible to help conduct heat away from the package. output data is now valid. Electrically-insulating, thermally-conductive "pads" may be installed This device actually guarantees that digital output data will be valid for underneath the package. Devices should be soldered to boards rather than 10ns prior to the falling edge of EOC. Therefore, EOC can be used to latch "socketed", and of course, minimal air fl ow over the surface can greatly data into external registers that have appropriate setup times. Any other help reduce the package temperature. available timing edges, including a delayed EOC or the rising edge of the next EOC pulse, can also be used for this purpose. The falling edge of the start convert pulse, though irrelevant to device timing, can cause conversion errors if it occurs at certain times. Therefore, the recommended start convert pulse width is between 40 and 80ns or between 130 and 160ns. DATEL performs ADS-944 production testing at the full 5MHz sampling rate using 80ns start convert pulses. N N+1 ~ START 80ns typ. CONVERT 10ns typ. Acquisition Time 115ns typ. Hold INTERNAL S/H 90ns max. Hold 60ns typ., ±10ns 35ns typ. Conversion Time EOC 150ns typ., 160ns max. INVALID 50ns typ., 60ns max. 140ns min., 150ns typ. DATA OUTPUT DATA N VALID DATA (N-1) VALID DATA Note: Scale is approximately 10ns per division. ~ START CONVERT pulse width: 40 to 80ns or 130 to 160ns. Figure 3. ADS-944 Timing Diagram DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 5 of 9 ADS-944 14-Bit, 5MHz Sampling A/D Converters PH vs. Input Frequency THD vs. Input Frequency 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 100 1000 10000 Frequency (kHz) Frequency (kHz) SNR vs. Input Frequency SNR+D vs. Input Frequency 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 100 1000 10000 Frequency (kHz) Frequency (kHz) Figure 4. Typical ADS-944 Dynamic Performance vs. Input Frequency at +25°C 0 +0.33 –10 –20 DNL (LSB's) –30 –40 –50 0 –60 –70 –80 –90 –0.55 –100 0 16,384 Digital Output Code –110 –120 –130 –140 0 250 500 750 1 1.25 1.5 1.75 2.0 2.25 2.5 kHz kHz kHz MHz MHz MHz MHz MHz MHz MHz Frequency (fin = 2.45MHz, fs = 5MHz, Vin = –0.5dB, 16,384 points) Figure 5. ADS-944 FFT 16,384 0 Digital Output Code Figure 6. ADS-944 Histogram and Differential Nonlinearity DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 6 of 9 Amplitude Relative to Full Scale (dB) SNR (dB) Peak Harmonic (–dB) SNR+D (dB) THD (–dB) Number of Occurences ADS-944 14-Bit, 5MHz Sampling A/D Converters DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 7 of 9 OPTION +15V +5VA SG5 SG6 C18 R3 0.1MFD OPTION P3 OPTION START 4 11 CONV. – 10 U4 P4 +5VF C24 5 CLC402 + 0.1MFD 6 HI2541 ANALOG ANA. IN OPTION IN +5VF C25 C19 + U6 0.1MFD 2.2MFD +5VF HCT7474 14 SG7 C17 SG8 OPTION SG9 4 0.1MFD +5VF +5V PR JPR3 2 5 L1 14 Q D 3 6 1 3 8 -5VA -15V X1 2 CK Q 1 5MHZ C22 20MHY CLR 7 + R4 1 C8 7 GND C1 C28 3 2.2MFD C27 3.2K C26 0.01MFD 2 U5 2.2MFD 2.2MFD 0.1MFD +15V 15PF 74HCT86 20 R1 2 19 +5V L2 3 1 1D Q1 3 18 2D Q2 START OFFSET 20K 4 17 CONV. 2 3D Q3 20MHY 5 16 -15V SG4 +15V +5V +5VA U1 4D Q4 C9 6 U3 15 C2 ADS-944 5D Q5 34 33 -5V 0.01MFD 7 74HCT 14 2.2MFD (MSB) B1 6D Q6 32 31 1 32 8 573 13 +5VA ST C21 (MSB) B1 30 29 7D Q7 +5V ANA. IN 2 31 9 12 -5V BIT1 L3 0.1MFD Q8 B2 28 27 3 30 8D 11 1 AIN BIT1 B3 LE OE 26 25 4 29 BIT2 GNDA B4 24 23 5 28 C23 20MHY OFF BIT3 GND 10 + B5 22 21 C10 6 27 +5VF C3 GNDA BIT4 B6 20 19 +15V 7 26 2.2MFD 0.01MFD 2.2MFD BIT5 GAIN B7 18 17 8 25 R2 BIT6 3 1 COMP B8 16 15 COMP 9 24 ENA BIT7 2 B9 14 13 L4 1 C16 GAIN 3 10 23 20K +5V BIT8 0.1MFD B10 12 11 2 11 22 26 25 BIT9 20 -15V JPR1 GNDA B11 10 9 24 23 12 21 2 19 20MHY +5V BIT10 +15V 1D Q1 B12 87 22 21 13 20 3 18 C4 C11 -15V BIT11 2D Q2 B1365 20 19 -5VA 14 19 4 17 2.2MFD 0.01MFD -5VA BIT12 3D Q3 (LSB) B1443 15 18 5 16 18 17 C20 BIT13 4D GNDD Q4 21 16 15 16 17 6 U2 15 0.1MFD JPR4 BIT14 EOC 5D Q5 P1 L5 14 13 7 74HCT 14 6D Q6 1 3 573 12 11 8 13 2 -5V -15V -5VA 7D Q7 9 12 10 9 20MHY 8D Q8 87 11 1 C5 C12 LE OE 65 -15V 2.2MFD 0.01MFD GND 10 43 +15V 21 L6 P2 20MHY C6 C13 2.2MFD 0.01MFD SG1 +5VA 9 8 L7 U5 10 SG2 74HCT86 20MHY C7 C14 SG3 2.2MFD 0.01MFD SG10 NOTES: 1. UNLESS OTHERWISE SPECIFIED ALL CAPACITORS ARE 50V. C1 - C6 ARE 20V. ALL RESISTORS ARE IN OHMS. 2. CLOSE SG1-SG3, SG9, SG10. Figure 7. ADS-944 Evaluation Board Schematic + + + + + + + + ADS-944 14-Bit, 5MHz Sampling A/D Converters 9000 8000 7000 The histogram in Figure 8 represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-944. 16.384 6000 conversions were processed with the input to the ADS-944 tied to analog ground. 5000 4000 3000 2000 1000 0 Digital Output Code Figure 8. ADS-944 Grounded Input Histogram DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 8 of 9 ccurences O ADS-944 14-Bit, 5MHz Sampling A/D Converters MECHANICAL DIMENSIONS INCHES (mm) 1.72 MAX. (43.69) Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 32 17 3 place decimal (.XXX) ±0.005 (±0.127) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating 1.11 MAX. over 100 microinches (nominal) nickel plating (28.19) 1 16 0.100 TYP. 0.235 MAX. (2.540) (5.969) 1.500 (38.100) 0.200 MAX. (5.080) +0.002 0.010 –0.001 (0.254) SEATING 0.190 MAX. 0.018 ±0.002 0.100 0.900 ±0.010 0.100 PLANE (4.826) (0.457) (2.540) (22.860) (2.540) 0.025 (0.635) 0.040 (1.016) ORDERING INFORMATION OPERATING MODEL NUMBER PACKAGE ROHS ACCESSORIES TEMP. RANGE ADS-944MC 0 to +70°C TDIP No ADS-B944 Evaluation Board (without ADS-944) ADS-944MC-C 0 to +70°C TDIP Yes HS-32 Heat Sink for all ADS-944 DDIP models ADS-944ME –40 to +100°C TDIP No ADS-944ME-C –40 to +100°C TDIP Yes ADS-944MM –55 to +125°C TDIP No ADS-944MM-C –55 to +125°C TDIP Yes ADS-944MM-QL –55 to +125°C TDIP No Receptacles for PC mounting can be ordered through AMP Inc., Part # 3-331272-8 (Component Lead Socket), 24 required. ADS-944MM-QL-C –55 to +125°C TDIP Yes ADS-944/883 –55 to +125°C TDIP No Contact DATEL for availability of surface-mount (J-lead) packaging or for MIL-STD-883 or DESC SMD product specifi cations. ADS-944-C/883 –55 to +125°C TDIP Yes 5962-9319801HXA –55 to +125°C TDIP No 5962-9319801HXC –55 to +125°C TDIP No 5962-9319803HXA –55 to +125°C TDIP No 5962-9319803HXC –55 to +125°C TDIP No DATEL is a registered trademark of DATEL, Inc. DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. ITAR and ISO 9001/14001 REGISTERED © 2015 DATEL, Inc. www.datel.com • e-mail: help@datel.com 21 Aug 2015 MDA_ADS-944.C01 Page 9 of 9