ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications PRODUCT OVERVIEW The functionally complete, easy-to-use ADS- Packaged in an industry-standard, 24-pin, CCD1201 is a 12-bit, 1.2MHz Sampling A/D Con- ceramic DDIP, the ADS-CCD1201 requires ±15V (or verter whose performance and production testing ±12V) and +5V supplies and typically consumes have been optimized for use in electronic imaging 1.7 (1.4) Watts. The device is 100% production applications, particularly those employing charge tested for all critical performance parameters and coupled devices (CCD’s) as their photodetectors. available in commercial (0 to +70°C), industrial The ADS-CCD1201 delivers the lowest noise (–40 to +100°C), or HI-REL (–55 to +125°C) oper- (400μVrms) and the best differential nonlinearity ating temperature ranges. error (±0.35LSB max.) of any commercially avail- For those applications using correlated double able 12-bit A/D in its speed class. It can respond sampling, the ADS-CCD1201 can be supplied to full scale input steps (from empty to full well) without its internal sample-hold amplifi er. DATEL with less than a single count of error, and its input will also entertain discussions about including the FEATURES is immune to overvoltages that may occur due to CDS circuit internal to the ADS-CCD1201. Please „ Unipolar input range (0 to +10V) blooming. contact us for more details. „ 1.2MHz sampling rate INPUT/OUTPUT CONNECTIONS „ 4096-to-1 dynamic range (72.2dB) PIN FUNCTION PIN FUNCTION 1 BIT 12 (LSB) 24 –12V/–15V SUPPLY „ Low noise, 400μVrms (1/6 of an LSB) 2 BIT 11 23 GROUND „ Outstanding differential nonlinearity error 3 BIT 10 22 +12V/+15V SUPPLY (±0.35 LSB max.) 4 BIT 9 21 +10V REFERENCE OUT 5 BIT 8 20 ANALOG INPUT „ Small, 24-pin ceramic DDIP 6 BIT7 19 GROUND 7 BIT 6 18 NO CONNECT „ Low power, 1.7 Watts 8 BIT 5 17 NO CONNECT „ Operates from ±12V or ±15V supplies 9 BIT 4 16 START CONVERT 10 BIT 3 15 EOC „ Edge-triggered, no pipeline delay 11 BIT 2 14 GROUND 12 BIT 1 (MSB) 13 +5V SUPPLY BLOCK DIAGRAM – ANALOG INPUT 20 S/H + DAC S2 12 BIT 1 (MSB) S1 11 BIT 2 10 BIT 3 +10V REFERENCE 21 REF 9 BIT 4 8 BIT 5 DIGITAL 7 BIT 6 REGISTER CORRECTION 6 BIT 7 LOGIC 5 BIT 8 FLASH 4 BIT 9 ADC 3 BIT 10 BUFFER 2 BIT 11 REGISTER 1 BIT 12 (LSB) START CONVERT 16 TIMING AND CONTROL LOGIC EOC 15 13 17, 18 22 14, 19, 23 24 +5V SUPPLY NO CONNECT +12V/+15V SUPPLY GROUND –12V/–15V SUPPLY Figure 1. ADS-CCD1201 Functional Block Diagram DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 1 of 9 ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications ABSOLUTE MAXIMUM RATINGS PHYSICAL/ENVIRONMENTAL PARAMETERS LIMITS UNITS PARAMETERS MIN. TYP. MAX. UNITS +12V/+15V Supply (Pin 22) 0 to +16 Volts Operating Temp. Range, Case –12V/–15V Supply (Pin 24) 0 to –16 Volts ADS-CCD1201MC, GC, MC-C, GC-C 0 — +70 °C +5V Supply (Pin 13) 0 to +6 Volts ADS-CCD1201ME, GE, ME-C, GE-C –40 — +100 °C Digital Input (Pin 16) –0.3 to +VDD +0.3 Volts ADS-CCD1201MM, GM, MM-C, GM-C –55 — +125 °C Analog Input (Pin 20) –4 to +17 Volts ADS-CCD1201MM-QL, 883, MM-QL-C, 883-C –55 — +125 °C Lead Temp. (10 seconds) +300 °C Thermal Impedance θjc — 5 — °C/Watt θca — 24 — °C/Watt Storage Temperature Range –65 — +150 °C FUNCTIONAL SPECIFICATIONS Package Type 24-pin, metal-sealed, ceramic DDIP (TA = +25°C, ±Vcc = ±15V (or ±12V), +VDD = +5V, 1.2MHz sampling rate, and a Weight 0.42 ounces (12 grams) minimum 1 minute warmup ➀ unless otherwise specifi ed.) +25°C 0 TO +70°C –55 TO +125°C ANALOG INPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Input Voltage Range d — 0 to +10 — — 0 to +10 — — 0 to +10 — Volts Input Resistance 1 — — 1 — — 1 — — kΩ Input Capacitance — 7 15 — 7 15 — 7 15 pF DIGITAL INPUT Logic Levels Logic "1" +2.0 — — +2.0 — — +2.0 — — Volts Logic "0" — — +0.8 — — +0.8 — — +0.8 Volts Logic Loading "1" — — +20 — — +20 — — +20 μA Logic Loading "0" — — –20 — — –20 — — –20 μA Start Convert Positive Pulse Width ➂ — 100 — — 100 — — 100 — ns STATIC PERFORMANCE Resolution — 12 — — 12 — — 12 — Bits Integral Nonlinearity (fi n = 10kHz) — ±0.5 — — ±0.5 — — ±1 — LSB Differential Nonlinearity (fi n = 10kHz) — +0.25 ±0.35 — ±0.25 ±0.35 — ±0.35 ±0.75 LSB Full Scale Absolute Accuracy — +0.1 ±0.3 — ±0.2 ±0.5 — ±0.3 ±0.5 %FSR Offset Error (Tech Note 2) — ±0.05 ±0.15 — ±0.1 ±0.15 — ±0.15 ±0.4 %FSR Gain Error (Tech Note 2) — ±0.1 ±0.3 — ±0.2 ±0.5 — ±0.3 ±0.5 % No Missing Codes (fi n = 10kHz) 12 — — 12 — — 12 — — Bits DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 100kHz — –86 –80 — –86 –80 — –82 –76 dB 100kHz to 500kHz — –84 –78 — –84 –78 — –81 –75 dB Total Harmonic Distortion (–0.5dB) dc to 100kHz — –84 –79 — –84 –79 — –77 –71 dB 100kHz to 500kHz — –82 –77 — –82 –77 — –76 –70 dB Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 100kHz 72 73 — 72 73 — 70 72 — dB 100kHz to 500kHz 71 72 — 71 72 — 70 72 — dB Signal-to-Noise Ratio f (& distortion, –0.5dB) dc to 100kHz 71 73 — 71 73 — 68 71 — dB 100kHz to 500kHz 71 72 — 71 72 — 68 71 — dB Two-Tone Intermodulation Distortion (fi n = 100kHz, 240kHz, fs = 1.2MHz, –0.5dB) — –85 — — –84 — — –83 — dB Noise — 400 — — 500 — — 700 — μVrms Input Bandwidth (–3dB) Small Signal (–20dB input) — 7.5 — — 7.5 — — 7.5 — MHz Large Signal(–0.5dB input) — 6 — — 6 — — 6 — MHz Feedthrough Rejection (fi n = 500kHz) — 84 — — 84 — — 84 — dB Slew Rate — ±60 — — ±60 — — ±60 — V/μs Aperture Delay Time — ±20 — — ±20 — — ±20 — ns Aperture Uncertainty — 5 — — 5 — — 5 — ps rms S/H Acquisition Time (to ±0.01%FSR, 10V step) 360 400 440 360 400 440 360 400 440 ns Overvoltage Recovery Time ➄ — 300 — — 300 — — 300 — ns A/D Conversion Rate 1.2 — — 1.2 — — 1.2 — — MHz ANALOG OUTPUT Internal Reference Voltage +9.95 +10.0 +10.05 +9.95 +10.0 +10.05 +9.95 +10.0 +10.05 Volts Drift — ±5 — — ±5 — — ±5 — ppm/ºC External Current — — 1.5 — — 1.5 — — 1.5 mA DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 2 of 9 ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications +25°C 0 TO +70°C –55 TO +125°C DIGITAL OUTPUTS MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Logic Levels Logic "1" +2.4 — — +2.4 — — +2.4 — — Volts Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts Logic Loading "1" — — –4 — — –4 — — –4 mA Logic Loading "0" — — +4 — — +4 — — +4 mA Delay, Falling Edge of EOC to Output Data Valid — — 35 — — 35 — — 35 ns Output Coding Straight Binary POWER REQUIREMENTS, ±15V Power Supply Range +15V Supply +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 Volts –15V Supply –14.5 –15.0 –15.5 –14.5 –15.0 –15.5 –14.5 –15.0 –15.5 Volts +5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 Volts Power Supply Current +15V Supply — +50 +65 — +50 +65 — +50 +65 mA –15V Supply — –40 –50 — –40 –50 — –40 –50 mA +5V Supply — +70 +85 — +70 +85 — +70 +85 mA Power Dissipation — 1.7 1.9 — 1.7 1.9 — 1.7 1.9 Watts Power Supply Rejection — — ±0.01 — — ±0.01 — — ±0.01 %FSR/%V POWER REQUIREMENTS Power Supply Range Power Supply Range +12V Supply +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 Volts –12V Supply –11.5 –12.0 –12.5 –11.5 –12.0 –12.5 –11.5 –12.0 –12.5 Volts +5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 Volts Power Supply Current +12V Supply — +50 +65 — +50 +65 — +50 +65 mA –12V Supply — –40 –48 — –40 –48 — –40 –48 mA +5V Supply — +70 +80 — +70 +80 — +70 +80 mA Power Dissipation — 1.4 1.6 — 1.4 1.6 — 1.4 1.6 Watts Power Supply Rejection — — ±0.01 — — ±0.01 — — ±0.01 %FSR/%V Footnotes: ➀ All power supplies must be on before applying a start convert pulse. All supplies ➃ Effective bits is equal to: and the clock (START CONVERT) must be present during warmup periods. Full Scale Amplitude The device must be continuously converting during this time. There is a slight (SNR + Distortion) – 1.76 + 20 log Actual Input Amplitude degradation in performance when using ±12V supplies. ➁ Contact DATEL for other input voltage ranges. 6.02 ➂ A 100ns wide start convert pulse is used for all production testing. ➄ This is the time required before the A/D output data is valid after the analog input is back within the specifi ed range. TECHNICAL NOTES 1. Obtaining fully specifi ed performance from the ADS-CCD1201 requires curacy and drift specifi cations may not be met, and loading the circuit may careful attention to pc-card layout and power supply decoupling. The cause accuracy errors within the converter. device’s analog and digital ground systems are connected to each other 4. A passive bandpass fi lter is used at the input of the A/D for all production internally. For optimal performance, tie all ground pins (14, 19, and 23) testing. directly to a large analog ground plane beneath the package. 5. Applying a start pulse while a conversion is in progress (EOC = logic "1") Bypass all power supplies, as well as the REFERENCE OUTPUT (pin 21), initiates a new and inaccurate conversion cycle. Data for the interrupted to ground with 4.7μF tantalum capacitors in parallel with 0.1μF ceramic and subsequent conversions will be invalid. capacitors. Locate the bypass capacitors as close to the unit as possible. If the user-installed offset and gain adjusting circuit shown in Figure 2 is INPUT VOLTAGE ZERO ADJUST GAIN ADJUST used, also locate it as close to the ADS-CCD1201 as possible. RANGE +½ LSB +FS –1½ LSB 2. ADS-CCD1201 achieves its specifi ed accuracies without external calibra- 0 to +10V +1.2207mV +9.99634V tion. If required, the device’s small initial offset and gain errors can be Table 1. Zero and Gain Adjust reduced to zero using the input circuit of Figure 2. When using this circuit, or any similar offset and gaincalibration hardware, make adjustments fol- lowing warmup. To avoid interaction, always adjust offset before gain. 3. When operating the ADS-CCD1201 from ±12V supplies, do not drive external circuitry with the REFERENCE OUTPUT (pin 21). The reference’s ac- DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 3 of 9 ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications devices do not overheat. The ground and power planes beneath the pack- CALIBRATION PROCEDURE (Refer to Figures 2 and 3) age, as well as all pcb signal runs to and from the device, should be as Any offset and/or gain calibration procedures should not be implemented heavy as possible to help conduct heat away from the package. Electrically until devices are fully warmed up. To avoid interaction, offset must be ad- insulating, thermally conductive "pads" may be installed underneath the justed before gain. The ranges of adjustment for the circuit of Figure 2 are package. Devices should be soldered to boards rather than "socketed," and guaranteed to compensate for the ADS-CCD1201’s initial accuracy errors of course, minimal air fl ow over the surface can greatly help reduce the and may not be able to compensate for additional system errors. package temperature. All fi xed resistors in Figure 2 should be metal-fi lm types, and multi-turn po- tentiometers should have TCR’s of 100ppm/°C or less to minimize drift with +15V temperature. In many applications, the CCD will require an offset-adjust (black balance) circuit near its output and also a gain stage, presumably 20k7 200k7 2k7 ZERO/ with adjust capabilities, to match the output voltage of the CCD to the input OFFSET ADJUST range of the A/D. If one is performing a "system I/O calibration" (from light GAIN in to digital out), these circuits can be used to compensate for the relatively ADJUST –15V +15V small initial offset and gain errors of the A/D. This would eliminate the need for the circuit shown in Figure 2. 1.98k 7 SIGNAL INPUT To Pin 20 of 507 ADS-CCD1201 A/D converters are calibrated b positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This can –15V be accomplished by connecting LED’s to the digital outputs and adjusting Figure 2. ADS-CCD1201 Calibration Circuit until certain LED’s "fl icker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. For the ADS-CCD1201, offset adjusting is normally accomplished at the point where all output bits are 0’s and the LSB just changes from a 0 to a 1. 13 +5V This digital output transition ideally occurs when the applied analog input is + 4.7μF 0.1μF 12 BIT 1 (MSB) +1/2LSB (+1.2207mV). 11 BIT 2 14 10 BIT 3 Gain adjusting is accomplished when all bits are 1’s and the LSB just 9 BIT 4 changes from a 1 to a 0. This transition ideally occurs when the analog 8 BIT 5 –12V/–15V 24 input is at +full scale minus 1 1/2 LSB’s (+9.99634V). 7 BIT 6 4.7μF 0.1μF + ADS-CCD1201 6 BIT 7 19, 23 Offset Adjust Procedure 5 BIT 8 4.7μF 0.1μF 4 BIT 9 + 1. Apply a train of pulses to the START CONVERT input (pin 16) so the con- 22 +12V/+15V 3 BIT 10 verter is continuously converting. If using LED’s on the outputs, a 200kHz 2 BIT 11 ANALOG 0 to +10V conversion rate will reduce fl icker. 20 INPUT 1 BIT 12 (LSB) 21 +10V REF. OUT 2. Apply +1.2207mV to the ANALOG INPUT (pin 20). + 0.1μF 4.7μF 15 EOC 3. Adjust the offset potentiometer until the output bits are 0000 0000 17, 18 00000 and the LSB fl ickers between 0 and 1. NO CONNECT Gain Adjust Procedure Figure 3. Typical ADS-CCD1201 Connection Diagram 1. Apply +9.99634V to the ANALOG INPUT (pin 20). 2. Adjust the gain potentiometer until all output bits are 1’s and the LSB fl ickers between 1 and 0. DIGITAL OUTPUT INPUT VOLTAGE UNIPOLAR (0 TO +10V) SCALE MSB LSB THERMAL REQUIREMENTS +9.9976 +FS – 1LSB 1111 1111 1111 All DATEL sampling A/D converters are fully characterized and speci- +7.5000 +3/4 FS 1100 0000 0000 fi ed over operating temperature (case) ranges of 0 to +70°C and – 55 +5.0000 +1/2 FS 1000 0000 0000 to +125°C. All room-temperature (TA = +25°C) production testing is +2.5000 +1/4 FS 0100 0000 0000 performed without the use of heat sinks or forced-air cooling. Thermal +0.0024 +1LSB 0000 0000 0001 impedance fi gures for each device are listed in their respective specifi ca- 0 0 0000 0000 0000 tion tables. Table 2. ADS-CCD1201 Output Coding These devices do not normally require heat sinks, however, standard Coding is straight binary; 1LSB = 2.44mV precautionary design and layout procedures should be used to ensure DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 4 of 9 ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications N N+1 START CONVERT 100ns 100ns typ. typ. 10ns typ. 10ns typ. Acquisition Time INTERNAL S/H 433ns typ. 400ns typ. Hold 60ns min.,70ns typ., 80ns max. 90ns typ. 420ns EOC Conversion Time 35ns max. 73ns max. OUTPUT DATA (N-1) VALID DATA N VALID DATA 760ns min. INVALID DATA Note: Scale is approximately 25ns per division. Figure 4. ADS-CCD1201 Timing Diagram TIMING throughput rate. It does not require multiple start convert pulses to bring valid The ADS-CCD1201 is an edge triggered device. A conversion is initiated by the digital data to its output pins. rising edge of the start convert pulse and no additional external timing signals are required. The device does not employ "pipeline" delays to increase its C2 15pF COG +15V R5 R3 12 2K .1% 200K 5% OFFSET 11 R2 U4 13 +5V ADJ C16 20K C1 0.1MF +15V 0.1MF 74LS86 U2 74LS240 -15V 20 SG2 B1 2 18 C4 1A1 1Y1 32 33 C3 P4 2.2MF R4 16 B2 SG3 4 0.1MF 1A2 1Y2 30 31 R1 50 1.98K 7 ANALOG 2 14 B3 6 – 1Y3 28 MSB INPUT 1A3 29 6 0.1% GAIN U5 8 12 B4 +5V 3 1A4 1Y4 26 27 ADJ R6 AD845 + 9 4 11 B5 2K 0.1% 24 2A1 2Y1 25 13 7 B6 2A2 2Y2 22 23 J5 C6 C7 C8 C21 C5 15 5 B7 0.1MF 2.2MF 2A3 2Y3 20 21 +15V 0.1MF 2.2MF 0.1MF R7 17 3 2A4 2Y4 19 -15V 10K 0.1% 19 1 ADS-CCD1201/1202 2G 1G R8 13 12 7 2 10K +5V B3 C19 C20 10 – 6 14 11 2.2MF 0.1MF DGND B4 0.1% U6 OP-77 3 15 10 +5V P2 EOC + B5 C17 4 16 9 U3 0.1MF ST. CONV B6 P1 17 8 74LS240 +5V B2 C23 B7 20 C22 0.1MF B8 2 1 18 7 2 18 2.2 18 17 B1 U1 B8 1A1 1Y1 4 3 MF 19 6 16 B9 -15V 4 16 15 AGND 1A2 1Y2 B9 C9 6 5 20 5 6 14 B10 14 13 C10 2.2MF INPUT 1A3 1Y3 B10 0.1MF 4 12 8 7 21 8 B11 12 11 +10VREF B11 1A4 1Y4 22 3 11 9 B12 -15V 10 +15V +15V 2A1 2Y1 9 B12 10 9 C12 C11 23 2 13 7 B13 8 7 AGND 2A2 2Y2 0.1MF B13 2.2MF 12 11 1 B14 24 15 5 -15V B14 2A3 2Y3 6 LSB 5 14 13 -15V C14 17 3 2A4 2Y4 4 EOC 3 C13 2.2MF 16 15 0.1MF 19 1 +15V 2 ST.CONV. 2G 1G 1 18 17 +5V 10 34 ENABLE 20 19 C15 0.1MF 4 22 21 6 U4 P3 5 J3 24 23 14 J1 9 25 J4 1 74LS86 START 8 3 U4 10 J2 26 CONVERT U4 2 74LS86 C24 74LS86 7 SG1 + Y1 2.2MF NOTES: 1 14 1. FOR ADS-BCCD1201 Y1 IS 1.2MHZ SEE NOTE 1 XTAL C18 FOR ADS-BCCD1202 Y1 IS 2MHZ 0.1MF 7 8 +5V Figure 5. ADS-CCD1201 Evaluation Board Schematic DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 5 of 9 + + + + + + + + ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 60 120 180 240 300 360 420 480 540 600 Frequency (kHz) Figure 6. ADS-CCD1201 FFT (Ţ n = 480kHz, fs = 1.2MHz, Vin = –0.5dB, 16,384 points) SNR vs. Input Frequency Peak Harmonics vs. Input Frequency 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 100 1000 10000 Input Frequency (kHz) Input Frequency (kHz) THD vs. Input Frequency SNR+D vs. Input Frequency 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 100 1000 10000 Input Frequency (kHz) Input Frequency (kHz) Figure 7. Typical ADS-CCD1201 Dynamic Performance vs. Input Frequency at +25°C (Vin = –0.5dB, fs = 1.2MHz) DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 6 of 9 SNR+D (dB) SNR (dB) Amplitude Relative to Full Scale (dB) THD (–dB) Peak Harmonic (–dB) ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications 4000 3500 3000 2500 This histogram represents the typical 2000 peak-to-peak noise (including quantization noise) associated with the ADS-CCD1201. 4,096 1500 conversions were processed with the input to the ADS-CCD1201 tied to 1000 analog ground. 500 0 Digital Output Code Figure 8. ADS-CCD1201 Grounded Input Histogram +0.15 0 –0.19 0 4096 Digital Output Code 0 4096 Digital Output Code Figure 9. ADS-CCD1201 Histogram and Differential Nonlinearity DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 7 of 9 Number of Occurences Number of Occurences DNL (LSB's) ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications MECHANICAL DIMENSIONS INCHES (mm) 1.31 MAX. (33.27) 24-PIN DDIP Dimension Tolerances (unless otherwise indicated): 24 2 place decimal (.XX) ±0.010 (±0.254) 13 3 place decimal (.XXX) ±0.005 (±0.127) 0.80 MAX. Lead Material: Kovar alloy (20.32) 50 microinches (minimum) Lead Finish: 12 1 gold plating over 100 microinches (nominal) nickel plating 0.100 TYP. (2.540) 1.100 (27.940) 0.235 MAX. (5.969) 0.200 MAX. (5.080) +0.002 0.010 –0.001 (0.254) 0.190 MAX. 0.100 0.100 (4.826) (2.540) (2.540) 0.600 ±0.010 SEATING PLANE (15.240) 0.040 0.018 ±0.002 0.025 (1.016) (0.457) (0.635) 1.31 MAX. (33.02) 24-PIN SURFACE MOUNT (unless otherwise indicated): Dimension Tolerances 24 13 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) Lead Material: Kovar alloy 0.80 MAX. (20.32) Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 1 12 0.020 TYP. 0.060 TYP. 0.015 (0.508) (1.524) 0.190 MAX. (0.381) (4.826) 0.130 TYP. MAX. radius PIN 1 for any pin (3.302) INDEX 0.100 (2.540) 0.020 0.010 TYP. (0.508) (0.254) 0.100 TYP. 0.040 (2.540) (1.016) DATEL, Inc. 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 8 of 9 ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications ORDERING INFORMATION OPERATING MODEL NUMBER PACKAGE ROHS ACCESSORIES TEMP. RANGE ADS-CCD1201MC 0 to +70°C DDIP No ADS-BCCD1201 Evaluation Board (without ADS-CCD1201) ADS-CCD1201MC-C 0 to +70°C DDIP Yes HS-24 Heat Sink for all ADS-CCD1201 models ADS-CCD1201ME –40 to +100°C DDIP No ADS-CCD1201ME-C –40 to +100°C DDIP Yes ADS-CCD1201MM –55 to +125°C DDIP No ADS-CCD1201MM-C –55 to +125°C DDIP Yes ADS-CCD1201MM-QL –55 to +125°C DDIP No ADS-CCD1201MM-QL-C –55 to +125°C DDIP Yes ADS-CCD1201/883 –55 to +125°C DDIP No ADS-CCD1201-C/883 –55 to +125°C DDIP Yes ADS-CCD1201GC 0 to +70°C SMT No ADS-CCD1201GC-C 0 to +70°C SMT Yes ADS-CCD1201GE –40 to +100°C SMT No ADS-CCD1201GE-C –40 to +100°C SMT Yes ADS-CCD1201GM –55 to +125°C SMT No ADS-CCD1201GM-C –55 to +125°C SMT Yes ADS-CCD1201G/883 –55 to +125°C SMT No ADS-CCD1201G-C/883 –55 to +125°C SMT Yes Receptacles for pc board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 24 required. Contact DATEL for availability of surface-mount packaging or high-reliability screening. DATEL is a registered trademark of DATEL, Inc. DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of 11 Cabot Boulevard, MansŢ eld, MA 02048-1151 USA licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. ITAR and ISO 9001/14001 REGISTERED © 2015 DATEL, Inc. www.datel.com • e-mail: help@datel.com 11 Sep 2015 MDA_ADS-CCD1201.C01 Page 9 of 9