LV77D Series 3.3 V LVDS Clock Oscillators February 2016 • Pletronics’ LV77D Series is a quartz crystal • 5 x 7 mm LCC Ceramic Package controlled precision square wave generator with • Enable/Disable Function on pad 1 an LVDS output. • Disable function includes low standby power • The package is designed for high density surface mode mount designs. • Low Jitter • Low cost mass produced oscillator. • 80 MHz ~ 325 MHz • Tape and Reel or cut tape packaging is available. Pletronics Inc. certifies this device is in accordance with the RoHS 6/6 (2011/65/EC) and WEEE (2002/96/EC) directives. Pletronics Inc. guarantees the device does not contain the following: Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s W eight of the Device: 0.16 grams Moisture Sensitivity Level: 1 As defined in J-STD-020D.1 Second Level Interconnect code: e4 Absolute Maximum Ratings: Parameter Unit V Supply Voltage -0.5V to +5.0V CC Vi Input Voltage -0.5V to V + 0.5V CC Vo Output Voltage -0.5V to V + 0.5V CC Thermal Characteristics o The maximum die or junction temperature is 155 C o The thermal resistance junction to board is 30 to 50 C/W att depending on the solder pads, ground plane and construction of the PCB. Product information is current as of publication date. The product conforms Copyright © 2011, Pletronics Inc. to specifications per the terms of the Pletronics standard warranty. Production processsing does not necessarily include testing of all parameters. LV77D Series 3.3 V LVDS Clock Oscillators February 2016 Part Number: LV77 45 D E V - 125. 0M - XX Part Marking: PLE LV77 Packaging code or blank FF.FFF M T250 = 250 per Tape and Reel C YMDXX T500 = 500 per Tape and Reel T1K = 1000 per Tape and Reel or Frequency in MHz LV7XYW W XX FF.FFF M Supply Voltage V CC C PLE XXX V = 3.3V + _ 10% Optional Enhanced OTR o Blank = Temp. range -10 to +70 C o C = Temp. range -20 to +70 C o E = Temp. range -40 to +85 C Series Model Frequency Stability 45 = + _ 50 ppm 44 = + _ 25 ppm 20 = + _ 20 ppm Series Model Marking Legend: PLE = Pletronics FF.FFF M = Frequency in MHz YYW W or YW W or YMD = Date of Manufacture (year and week, or year-month-day) All other marking is internal factory codes Specifications such as frequency stability, supply voltage and operating temperature range, etc. are not identified from the marking. External packaging labels and packing list will correctly identify the ordered Pletronics part number. Codes for Date Code YMD Code Code 45678 A B CD E F G H J K LM Year20142015201620172018MonthJANFEBMARAPRMAYJUNJULAUGSEPOCTNOVDEC Code 1 2 3 4 5 6 7 8 9 A B C D EF G Day 12345678910111213141516 Code HJKLMNPRTUVWXYZ Day171819202122232425262728293031 www.pletronics.com 425-776-1880 2 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 Electrical Specification for 3.30V + _10% over the specified temperature range and the frequency range of 80 to 325 MHz Item Min Max Unit Condition -50 +50 ppm For all supply voltages, load changes, aging for 1 Frequency Accuracy “45" year, shock, vibration and temperatures “44" -25 +25 -20 +20 “20" Output Waveform LVDS Output High Level -- 1.60 Volts - Output Low Level 0.90 -- Volts - Differential Output (V ) 250 450 mVolts - OD See load circuit R1 = 50 ohms Output Offset Voltage (V ) 1.125 1.375 Volts > 80 MHz OS 1.125 1.500 Volts < 80 MHz Differential Output Error (dV ) -- 50 mVolts - OS Output Symmetry 45 55 % Referenced to 50% of amplitude or crossing point Output T and T 300 700 pS > 80 MHz RISE FALL Vth is 20% and 80% of waveform 400 900 pS < 80 MHz Jitter - 0.6 pS RMS Measured from 12KHz to 20MHz from Fnominal - 2.8 Measured from 10Hz to 1MHz from Fnominal Vcc Supply Current - 66 mA > 80 MHz Includes current of properly terminated device - 45 mA < 80 MHz Enable/Disable Internal Pull-up 50 - Kohm To Vcc (equivalent resistance) V disable - 0.8 Volts Referenced to Ground V enable 2.0 - Volts Referenced to Ground Output leakage V = V -10 +10 uA Pad 1 low, device disabled OUT CC V = 0V -10 +10 uA OUT Enable time - 2 mS Time for output to reach a logic state Disable time - 200 nS Time for output to reach a high Z state Start up time - 5 mS > 80 MHz Measured from the time Vcc = 3.0V - 3 mS < 80 MHz o Operating Temperature Range -10 +70 C Standard Temperature Range o -20 +70 C Extended Temperature Range “C” Option o -40 +85 C Extended Temperature Range “E” Option o Storage Temperature Range -55 +125 C Standby Current I - 3 uA > 80 MHz CC Pad 1 low, device disabled - 1.5 mA < 80 MHz Specifications with Pad 1 E/D open circuit www.pletronics.com 425-776-1880 3 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 Typical Phase-Noise Response Load Circuit Test Waveform www.pletronics.com 425-776-1880 4 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 Reliability: Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002, Condition B Vibration MIL-STD-883 Method 2007, Condition A Solderability MIL-STD-883 Method 2003 Thermal Shock MIL-STD-883 Method 1011, Condition A ESD Rating Model Minimum Voltage Conditions Human Body Model 1500 MIL-STD-883 Method 3115 Charged Device Model 1000 JESD 22-C101 Package Labeling Label is 1" x 2.6" (25.4mm x 66.7mm) Label is 1" x 2.6" (25.4mm x 66.7mm) Font is Courier New Font is Arial Bar code is 39-Full ASCII www.pletronics.com 425-776-1880 5 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 Mechanical: Inches mm A 0.276 + _0.006 7.00 + _0.15 B 0.197 + _0.006 5.00 + _0.15 C 0.067 max 1.70 max 1 D 0.038 0.96 1 E 0.200 5.08 1 F 0.004 0.10 1 G 0.050 1.27 1 H 0.055 1.40 1 I 0.024 0.60 Contacts (pads): 1 1 Typical dimensions J 0.004R 0.10R Gold 11.8 to 39.4µinches (0.3 to 1.0µm) over 1 Not to Scale K 0.008R 0.20R Nickel 50 to 350 µinches (1.27 to 8.89 µm) Pad Function Note 1 Output When this pad is not connected the oscillator shall operate. Enable/Disable When this pad is <0.30 volts, the output will be inhibited (high impedance state.) Recommend connecting this pad to V if the oscillator is to be always on. CC 2 No connect There is no internal connection to this pad 3 Ground (GND) 4 Output The outputs must be terminated, 100 ohms between the outputs is the ideal termination. 5 Output* 6 Supply Voltage Recommend connecting appropriate power supply bypass capacitors as close as (V ) possible. CC Layout and application information Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both input pads For Optimum Jitter Performance, Pletronics recommends: • a ground plane under the device • no large transient signals (both current and voltage) should be routed under the device • do not layout near a large magnetic field such as a high frequency switching power supply • do not place near piezoelectric buzzers or mechanical fans. www.pletronics.com 425-776-1880 6 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 Reflow Cycle (typical for lead free processing) The part may be reflowed 3 times without degradation. Tape and Reel: available for quantities of 250 to 1000 per reel, cut tape for < 250 Constant Dimensions Table 1 T1 Tape D1 S1 T D0 E1 P0 P2 Max Size Min Min Max 8mm 1.0 2.0 + _0.05 1.5 12mm 1.5 1.75 4.0 0.6 0.6 0.1 +0.1 + _0.1 + _0.1 16mm 1.5 2.0 -0.0 + _0.1 24mm 1.5 Variable Dimensions Table 2 Tape B1 E2 Min F P1 T2 W Ao, Bo & Size Max Max Max Ko 16 mm 12.1 14.25 7.5 + _0.1 8.0 + _0.1 8.0 16.3 Note 1 Note 1: Embossed cavity to conform to EIA-481-B Dimensions in mm Not to scale REEL DIMENSIONS A inches 7.0 10.0 13.0 mm 177.8 254.0 330.2 B inches 2.50 4.00 3.75 mm 63.5 101.6 95.3 Tape Width C mm 13.0 +0.5 / -0.2 D mm 16.4 16.4 16.4 16.0 +2.0 +2.0 +2.0 -0.0 -0.0 -0.0 Reel dimensions may vary from the above www.pletronics.com 425-776-1880 7 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 IMPORTANT NOTICE Pletronics Incorporated (PLE) reserves the right to make corrections, improvements, modifications and other changes to this product at anytime. PLE reserves the right to discontinue any product or service without notice. Customers are responsible for obtaining the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to PLE’s terms and conditions of sale supplied at the time of order acknowledgment. PLE warrants performance of this product to the specifications applicable at the time of sale in accordance with PLE’s limited warranty. Testing and other quality control techniques are used to the extent PLE deems necessary to support this warranty. Except where mandated by specific contractual documents, testing of all parameters of each product is not necessarily performed. PLE assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using PLE components. To minimize the risks associated with the customer products and applications, customers should provide adequate design and operating safeguards. PLE products are not designed, intended, authorized or warranted to be suitable for use in life support applications, devices or systems or other critical applications that may involve potential risks of death, personal injury or severe property or environmental damage. Inclusion of PLE products in such applications is understood to be fully at the risk of the customer. Use of PLE products in such applications requires the written approval of an appropriate PLE officer. Questions concerning potential risk applications should be directed to PLE. PLE does not warrant or represent that any license, either express or implied, is granted under any PLE patent right, copyright, artwork or other intellectual property right relating to any combination, machine or process which PLE product or services are used. Information published by PLE regarding third-party products or services does not constitute a license from PLE to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from PLE under the patents or other intellectual property of PLE. Reproduction of information in PLE data sheets or web site is permissible only if the reproduction is without alteration and is accompanied by associated warranties, conditions, limitations and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. PLE is not responsible or liable for such altered documents. Resale of PLE products or services with statements different from or beyond the parameters stated by PLE for that product or service voids all express and implied warranties for the associated PLE product or service and is an unfair or deceptive business practice. PLE is not responsible for any such statements. Contacting Pletronics Inc. Pletronics Inc. Tel: 425-776-1880 th 19013 36 Ave. W est Fax: 425-776-2760 Lynnwood, WA 98036-5761 USA E-mail: ple-sales@pletronics.com URL: www.pletronics.com Copyright © 2006, 2007, 2010, 2011, Pletronics Inc. www.pletronics.com 425-776-1880 8 LV77D Series 3.3 V LVDS Clock Oscillators February 2016 PLETRONICS INC. DOCUMENT CONTROL This is the document control page. This is not printed or part of the PDF that can be downloaded on the web site. This is to keep the history of the datasheet document and all revisions. Part Number Family: LV77D Document File Name: LV77D 3.3V.wpd PDF File Name: LV77D 3.3V.pdf Written By: R Gubser Approved By: Melody Mistlin and Claude Lee after sales and engineering group review. This specification was written around the NPC IC CF5037 for > 80 MHz and Anasem IC AS148xx for < 80 MHz and data taken at PLE about its performance. Revision History: April 2005 Initial Release June 2005 Added dual voltage marking code B, added IC code, deleted substitute note Jan 2006 Added 1-80 MHz specs per Anasem IC, updated to new process label & important notice Sept 2006 Updated marking page, RoHS label & mech shock & jitter to .6 from .15 Oct 2006 Added T250, etc. Changed height from 1.87 to 1.70 max Dec 2006 Deleted Frequency range April 2007 Changed std OTR to -10 from 0 on part number and table January 30, 2010 Added the limited frequencies available at <=80MHz Added a maximum thickness to the gold on the package rag April 26, 2010 Added the “C” temperature range, Added 3 times reflow rag January 28, 2011 Changed the upper frequency to 325MHz Rag February 28, 2014 Lower frequency changed to 80MHz (removed table of frequencies < 80). Changed enable/disable times to 2ms/200ns. July 6, 2015 Corrected typo in gold thickness on mechanical pages (39.4 uinches from 29.4) Typo, MM DK February 3, 2016 Updated date code range. Lower frequency on electrical specification page changed from 1 to 80. www.pletronics.com 425-776-1880 9